Alternatives and similar repositories for simbook

Users that are interested in simbook are comparing it to the libraries listed below

• syntacore / snippy
  ☆59Updated last week
• P3109 / Public
  materials available to the public
  ☆25Updated 6 months ago
• makslevental / mmlir
  A minimal (really) out-of-tree MLIR example
  ☆44Updated 3 weeks ago
• ArchC / ArchC
  A powerful and modern open-source architecture description language.
  ☆42Updated 7 years ago
• andrewt0301 / static-analysis-course
  Materials for the "Principles of Static Program Analysis" course
  ☆9Updated 6 months ago
• mwillsey / cs265
  Website for CS 265
  ☆28Updated 5 months ago
• iree-org / iree-bare-metal-arm
  Example for running IREE in a bare-metal Arm environment.
  ☆33Updated 3 months ago
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆48Updated 2 weeks ago
• openhwgroup / corev-llvm-project
  ☆15Updated 10 months ago
• IITH-Compilers / ML-Compiler-Bridge
  Library to interface Compilers and ML models for ML-Enabled Compiler Optimizations
  ☆18Updated 2 months ago
• daniellustig / riscv-memory-model
  A formalization of the RVWMO (RISC-V) memory model
  ☆33Updated 2 years ago
• llvm / eudsl
  Embedded Universal DSL: a good DSL for us, by us
  ☆37Updated this week
• ychen306 / vegen
  ☆29Updated 2 years ago
• epfl-vlsc / parendi
  Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU
  ☆22Updated last year
• EntityFX / anybench
  CPU Benchmarks Set
  ☆75Updated 10 months ago
• dzaima / intrinsics-viewer
  x86-64, ARM, and RVV intrinsics viewer
  ☆46Updated last month
• danlark1 / quadratic_strict_weak_ordering
  ☆31Updated 2 years ago
• Mogball / declarative-mlir-compiler
  Declarative MLIR compilers in Python!
  ☆35Updated 4 years ago
• syntacore / rvv-simulator
  RISC-V vector extension ISA simulation
  ☆16Updated 5 years ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆33Updated last month
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆42Updated last year
• true-grue / awesome-russian-cs-books
  ☆38Updated 3 years ago
• Fedex100 / awesome-compilers
  ☆15Updated 8 years ago
• montedalrymple / yrv
  Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.
  ☆18Updated 3 years ago
• gvsoc / gvsoc
  ☆19Updated this week
• intel / device-modeling-language
  ☆100Updated this week
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆31Updated 4 years ago
• aqjune / mlir-tv
  A translation validation framework for MLIR
  ☆85Updated 2 months ago
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆25Updated last year
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 3 years ago