代码在这个库里 Code is here
☆66Jan 28, 2026Updated last month
Alternatives and similar repositories for Kryon
Users that are interested in Kryon are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This project implemented an unoptimized simple convolutional neural network in ZYNQ's PL and realized data transmission through axidma dr…☆12Aug 5, 2018Updated 7 years ago
- Chinese Guide for Alveo Getting Started☆12May 18, 2020Updated 5 years ago
- 哈尔滨工业大学(深圳)2021年球季学期深度学习体系结构实验☆17Oct 1, 2022Updated 3 years ago
- Constrast limited adaptive histogram equlization based on Verilog☆40Jul 21, 2023Updated 2 years ago
- AI Chip project☆34Jul 14, 2021Updated 4 years ago
- Bitmap Processing Library & AXI-Stream Video Image VIP☆35Apr 11, 2022Updated 3 years ago
- ☆66Mar 14, 2023Updated 3 years ago
- hi3516dv300☆11Oct 20, 2021Updated 4 years ago
- Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database☆579Feb 19, 2021Updated 5 years ago
- RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor☆17Feb 17, 2026Updated last month
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆14Jul 23, 2020Updated 5 years ago
- ☆18Jun 19, 2021Updated 4 years ago
- Zynq/FPGA实现CNN手写数字(0-9)识别☆40Dec 14, 2024Updated last year
- Code for "Understanding Metastability in SAR ADCs: Part II: Asynchronous"☆11Apr 19, 2022Updated 3 years ago
- imx327 imx335☆31Dec 3, 2019Updated 6 years ago
- Xilinx IP repository☆13May 5, 2018Updated 7 years ago
- ALNS☆14May 12, 2023Updated 2 years ago
- This repository contains MATLAB code which can be used to generate simulink model and HDL code for implementation on FPGA. Since HDL code…☆13May 6, 2020Updated 5 years ago
- The VD100 development board is based on the Xilinx Versal AI Edge series chip xcve2302 and is designed with a core board and a bottom boa…☆18Jul 9, 2024Updated last year
- The Dark Channel Prior technique is implemented on FPGA using only Verilog code and no Intellectual Property, making it convenient to rep…☆59Jun 11, 2024Updated last year
- Hardware and software implementation of Sparsely-active SNNs☆22Mar 6, 2026Updated 2 weeks ago
- 本信号处理板主要由FPGA芯片和CYUSB3.0 芯片组成,其中FPGA模块主要完成与相关外设的交互,CYUSB3.0主要完成协议数据的传输。 2.2.1 FPGA模块 处理流程: 1. 链路初始化: 在上位机完成USB固件的下载,并读取…☆30Nov 9, 2015Updated 10 years ago
- AIChip 2021 project, NCKU☆17May 6, 2021Updated 4 years ago
- ☆11Jul 25, 2018Updated 7 years ago
- transplant several overlays to s9_pynq board☆17Oct 31, 2020Updated 5 years ago
- Digital Design Lab Spring 2019 Final Project☆13Jun 17, 2019Updated 6 years ago
- ISP☆13Nov 25, 2023Updated 2 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆23May 7, 2024Updated last year
- NMS_decode☆13Jul 17, 2020Updated 5 years ago
- Files associated with Digital Integrated Circuits (ecen4303) at Oklahoma State University☆10Dec 7, 2023Updated 2 years ago
- ☆11Feb 28, 2016Updated 10 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆231Oct 16, 2025Updated 5 months ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆165Dec 13, 2020Updated 5 years ago
- course design☆23Feb 28, 2018Updated 8 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- WACV 2025: Theory, Experiments, Dataset, and Code for our newly proposed LDR → HDR Deep Learning Dataset called GTA-HDR☆31Nov 21, 2025Updated 4 months ago
- Hardware accelerator for convolutional neural networks☆67Aug 9, 2022Updated 3 years ago
- The code about this final project (Online scheduling of image satellites based on deep reinforcement learning)☆21May 4, 2021Updated 4 years ago
- 包括同步FIFO(输入输出位宽相同),异步FIFO(输入输出位宽相同),异步FIFO(能实现输出数据位宽是输入数据位宽的1/2或2倍)☆23Nov 7, 2022Updated 3 years ago