Alternatives and similar repositories for ucoreonrv

Users that are interested in ucoreonrv are comparing it to the libraries listed below

• oscomp / os-competition-info
  "全国大学生操作系统比赛2025"相关信息
  ☆276Updated last week
• HUST-OS / xv6-k210
  Port XV6 to K210 board!
  ☆144Updated 4 years ago
• NJU-ProjectN / am-kernels
  AbstractMachine kernels
  ☆68Updated 3 months ago
• loongson-education / nscscc-wiki
  NSCSCC 信息整合
  ☆252Updated 4 years ago
• oscomp / testsuits-for-oskernel
  ☆142Updated 3 months ago
• sunshaoce / rvcc-course
  ☆94Updated last year
• plctlab / writing-your-first-riscv-simulator
  《从零开始的RISC-V模拟器开发》配套的PPT和教学资料
  ☆234Updated 4 years ago
• Silverster98 / bit_nscscc_suggestion
  为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助
  ☆133Updated 5 years ago
• TrivialCompiler / TrivialCompiler
  A toy compiler written in C++17 that translates SysY (a C-like toy language) into ARM-v7a assembly.
  ☆146Updated 4 years ago
• oscomp / 2021oscomp-best-kernel-design-impl
  2021年OS比赛获奖赛题（文档/代码开源），可用于2022年参赛同学的学习和提高
  ☆48Updated 3 years ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆145Updated last year
• Z-Y00 / Examples-in-book-write-your-own-cpu
  《自己动手写CPU》一书附带的文件
  ☆87Updated 7 years ago
• NJU-ProjectN / fceux-am
  ☆101Updated 2 weeks ago
• No-SF-Work / miniSysY-tutorial
  BUAASE2019级的编译实验的实验指导与实验安排
  ☆119Updated 3 years ago
• hehao98 / RISCV-Simulator
  A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation
  ☆197Updated last year
• zach0zhang / Single_instruction_cycle_OpenMIPS
  通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器
  ☆206Updated 3 years ago
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆37Updated 3 years ago
• xyongcn / LoongsonCsprj2017
  Computer System Project for Loongson FPGA Board in 2017
  ☆54Updated 7 years ago
• ustb-owl / MimiC
  MimiC is a compiler of C subset (extended SysY language) by USTB NSCSCC team.
  ☆62Updated 2 years ago
• howardlau1999 / yatcpu
  Yet another toy CPU.
  ☆93Updated last year
• arcsysu / SYsU-lang
  A mini, simple and modular compiler for SYsU/SysY(tiny C). Based on Clang/LLVM/ANTLR4/Bison/Flex.
  ☆220Updated last year
• sunshaoce / learning-riscv
  入门RISC-V的手册
  ☆61Updated last year
• luzhixing12345 / archlab
  NUDT 高级体系结构实验
  ☆35Updated last year
• NJU-ProjectN / nvboard
  NJU Virtual Board
  ☆295Updated 2 months ago
• sunshaoce / rvcc
  本课程基于Rui的chibicc，@sunshaoce和@ksco将其由原来的X86架构改写为RISC-V 64架构，同时加入了大量的中文注释，并且配有316节对应于每一个commit的课程，帮助读者可以层层推进、逐步深入的学习编译器的构造。
  ☆359Updated 2 years ago
• Martins3 / Martins3.github.io
  Scratchpad about Linux, Compiler and Virtualization
  ☆76Updated last year
• oscourse-tsinghua / LoongsonCsprj2017-manual
  基于龙芯FPGA开发板的计算机综合系统实验
  ☆26Updated 6 years ago
• shzhxh / xv6-riscv-book-CN
  xv6-riscv-book中译版
  ☆83Updated last year
• trivialmips / TrivialMIPS
  MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
  ☆108Updated 6 years ago
• jinhang1997 / Q-A-for-PA-2018
  PA2018常见问题解答（持续更新，更新频率1-2天/次），欢迎star
  ☆31Updated 7 years ago