64-bit RISC-V (RV64GC) core that boots Linux on an Arty A7 FPGA. Designed entirely by Claude Code: the specifications, RTL, verification and documents were all written by the AI.
☆80Oct 17, 2026Updated this week
Alternatives and similar repositories for mmRISC-2
Users that are interested in mmRISC-2 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Z-Core - A Lightweight RISC-V Processor (RV32IMZicsr)☆15Oct 4, 2026Updated 2 weeks ago
- Examples for using pyuvm☆23Jun 5, 2024Updated 2 years ago
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆52Jul 11, 2025Updated last year
- Declarative flat parsing engine. No AST - only SoA tables, zero-copy spans and SIMD/SWAR☆34Updated this week
- [Not Another DLL Injector] - a simple, all purpose DLL injector for x64 and x86☆12Jul 4, 2019Updated 7 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Simple UVM testbench development using the uvmtb_template files☆27Jan 16, 2025Updated last year
- Learning SIMD with Rust☆18Oct 8, 2026Updated last week
- ☆12Nov 3, 2021Updated 4 years ago
- ☆19Jun 2, 2025Updated last year
- The shortest path from PyTorch to custom ASICs.☆111Sep 26, 2026Updated 3 weeks ago
- ☆94Apr 12, 2026Updated 6 months ago
- Example of an ELF parser to learn about the ELF format☆11Oct 6, 2024Updated 2 years ago
- Inspired by Matt Parker's video: https://www.youtube.com/watch?v=_-AfhLQfb6w Best time: 1.23s☆14Dec 1, 2022Updated 3 years ago
- Dockerfile for AMD/Xilinx Vivado☆16Mar 22, 2026Updated 6 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆41Oct 7, 2026Updated last week
- A NES emulator written in Rust☆12Feb 24, 2026Updated 7 months ago
- ☆10Nov 8, 2019Updated 6 years ago
- Open Source Brain Platform | AI training and inference in Rust☆43Updated this week
- A Risc-V implementation for the Gowin FPGA board - Sipeed Tang Nano 20K☆39Jan 31, 2026Updated 8 months ago
- Claude Code mods that fix and translate your prompts before Claude reads them☆13Oct 6, 2026Updated last week
- Verification of an Asynchronous FIFO using UVM & SVA☆13Jun 26, 2025Updated last year
- A SystemVerilog-based simulation and design of a Last Level Cache (LLC) implementing the MESI protocol, featuring Pseudo-LRU replacement,…☆17Mar 8, 2026Updated 7 months ago
- Fault Injection Automatic Test Equipment☆17Nov 22, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆11Nov 17, 2025Updated 11 months ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a log…☆80Feb 12, 2026Updated 8 months ago
- Regex Engine using SIMD and Roaring-Bitmaps☆11Dec 26, 2022Updated 3 years ago
- Regionalized Value State Dependence Graph written in Rust☆13Nov 17, 2019Updated 6 years ago
- Warp Request for Comments - contracts standards☆11Nov 15, 2023Updated 2 years ago
- LLMxRay — Local LLM Observatory. Full observability interface for Ollama: chat, streaming, reasoning, RAG, introspection, metrics.☆23Updated this week
- 🏛️ University projects.☆16Feb 22, 2026Updated 7 months ago
- The presentation at Spark Summit 2014 showing how 4Quant does production scale image processing and analysis using Spark☆16Jul 29, 2014Updated 12 years ago
- ☆15Aug 8, 2022Updated 4 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Computable GPU Index (CGI): an open, verifiable price index for GPU compute, in USD per GPU-hour. Reproduce any published value from the …☆22Sep 24, 2026Updated 3 weeks ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆15Aug 26, 2024Updated 2 years ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆16Jan 14, 2021Updated 5 years ago
- GTKWave Decoders for RISCV☆15Aug 16, 2025Updated last year
- Easily control multiple GoPros with the web browser via Bluetooth, without additional hardware☆12Feb 28, 2024Updated 2 years ago
- Commodore VIC20 core for the Tang Nano 9K FPGA with LCD Output☆12Feb 16, 2025Updated last year
- Verilog HDL code and documentation for pipelined RISC-V processors designed as a minor project by a team of 4. Includes testbench files, …☆11Nov 23, 2023Updated 2 years ago