A lightweight IDE that supports verilog simulation and RISC-V code compilation
☆56Jul 26, 2022Updated 3 years ago
Alternatives and similar repositories for EveIDE_LIGHT
Users that are interested in EveIDE_LIGHT are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- some interpreters with high protability☆17Jul 10, 2022Updated 3 years ago
- A Model Context Protocol server for embedded debugging with probe-rs - supports ARM Cortex-M, RISC-V debugging via J-Link, ST-Link, and m…☆107Aug 6, 2025Updated 10 months ago
- "aura" my super-scalar O3 cpu core☆26May 25, 2024Updated 2 years ago
- Open-Source EDA workshop for RISC-V community☆12Jul 27, 2022Updated 3 years ago
- ☆19Aug 10, 2020Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Coffer is a RISC-V trusted execution environment developed in Rust.☆20Mar 3, 2022Updated 4 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- ☆16May 26, 2026Updated 2 weeks ago
- ☆14Oct 19, 2019Updated 6 years ago
- ☆13Dec 22, 2024Updated last year
- Using stereo vision 👀 to identify the obstacles by processing images on a FPGA☆21Feb 8, 2023Updated 3 years ago
- K210 YOLO_V2 FACE DETECTION☆23May 16, 2019Updated 7 years ago
- Открытое RISC-V процессорное ядро MIRISCV для образовательных целей☆30Dec 5, 2024Updated last year
- ☆24Nov 4, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆17Jun 2, 2026Updated last week
- data preprocessing scripts for gem5 output☆19May 23, 2025Updated last year
- Redesigned hardware of adamgreig's fpga/flash programmer☆22Apr 20, 2020Updated 6 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆39Nov 25, 2019Updated 6 years ago
- sipeed2022_spring_competition☆11Apr 16, 2022Updated 4 years ago
- 🍋: A General Lock following paper "Optimistic Lock Coupling: A Scalable and Efficient General-Purpose Synchronization Method"☆28Aug 31, 2021Updated 4 years ago
- ☆46Jul 20, 2019Updated 6 years ago
- DE1SoC VGA and Audio☆10Jan 11, 2017Updated 9 years ago
- A Rocket-Chip with a Dynamically Randomized LLC☆14Sep 18, 2024Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- PoC LoongArch - RISC-V emulator☆34Feb 17, 2026Updated 3 months ago
- Rust Hardware Abstraction Layer for Bouffalo chips☆23Sep 27, 2025Updated 8 months ago
- Ultra96 PYNQ入门之一次简单的总结☆14May 21, 2020Updated 6 years ago
- OpenCCA: An Open Framework to Enable Arm CCA Research☆22Sep 10, 2025Updated 9 months ago
- A python REPL and Editor and console based on Qt.☆14Mar 14, 2026Updated 2 months ago
- Jsmith, a random generator of Java programs☆16Updated this week
- Simple single-port AXI memory interface☆50Jun 7, 2024Updated 2 years ago
- ☆35May 21, 2026Updated 3 weeks ago
- ☆10Dec 28, 2020Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- USBMETER - A meter for detecting the current and voltage of USB bus.☆12Nov 17, 2024Updated last year
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆30Oct 3, 2023Updated 2 years ago
- SleepPanda, a caring sleep manager☆10May 5, 2023Updated 3 years ago
- Tiny Lander like Lunar Lander for ATTiny85 at 16MHz☆15Apr 14, 2023Updated 3 years ago
- ☆26Aug 10, 2023Updated 2 years ago
- a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog☆24Jul 20, 2023Updated 2 years ago
- 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.☆28Jan 6, 2023Updated 3 years ago