Adancurusul / EveIDE_LIGHTView external linksLinks
A lightweight IDE that supports verilog simulation and RISC-V code compilation
☆54Jul 26, 2022Updated 3 years ago
Alternatives and similar repositories for EveIDE_LIGHT
Users that are interested in EveIDE_LIGHT are comparing it to the libraries listed below
Sorting:
- A Model Context Protocol server for embedded debugging with probe-rs - supports ARM Cortex-M, RISC-V debugging via J-Link, ST-Link, and m…☆39Aug 6, 2025Updated 6 months ago
- Open-Source EDA workshop for RISC-V community☆12Jul 27, 2022Updated 3 years ago
- sipeed2022_spring_competition☆11Apr 16, 2022Updated 3 years ago
- Открытое RISC-V процессорное ядро MIRISCV для образовательных целей☆23Dec 5, 2024Updated last year
- ☆14Oct 19, 2019Updated 6 years ago
- ☆19Aug 10, 2020Updated 5 years ago
- Coffer is a RISC-V trusted execution environment developed in Rust.☆21Mar 3, 2022Updated 3 years ago
- ☆45Jul 20, 2019Updated 6 years ago
- Rust Hardware Abstraction Layer for Bouffalo chips☆23Sep 27, 2025Updated 4 months ago
- 本项目已迁移至https://github.com/ywz978020607/History☆25Nov 17, 2020Updated 5 years ago
- Redesigned hardware of adamgreig's fpga/flash programmer☆22Apr 20, 2020Updated 5 years ago
- "aura" my super-scalar O3 cpu core☆25May 25, 2024Updated last year
- K210 YOLO_V2 FACE DETECTION☆23May 16, 2019Updated 6 years ago
- VCD visualizer: view your waveforms in ASCII format, or export them to TikZ figures.☆32Nov 2, 2025Updated 3 months ago
- ☆32Jan 21, 2026Updated 3 weeks ago
- PoC LoongArch - RISC-V emulator☆33Updated this week
- 🍋: A General Lock following paper "Optimistic Lock Coupling: A Scalable and Efficient General-Purpose Synchronization Method"☆28Aug 31, 2021Updated 4 years ago
- Лабораторные работы по ЦОС (python)☆10Apr 28, 2025Updated 9 months ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆29Oct 3, 2023Updated 2 years ago
- SystemVerilog FSM generator☆33May 5, 2024Updated last year
- ☆30Dec 8, 2019Updated 6 years ago
- AXI4 BFM in Verilog☆35Dec 13, 2016Updated 9 years ago
- The program for USB-Blaster Chinese version on STM32 works with☆33Sep 7, 2017Updated 8 years ago
- Modern co-simulation framework for RISC-V CPUs☆171Updated this week
- Kernel Playground - A playground to run large scale experiments on the Linux Kernel☆16Nov 8, 2025Updated 3 months ago
- 基于RDK系列开发板的yolov5工具库。The yolov5 tool library is based on the RDK series development board.☆10Oct 31, 2024Updated last year
- SimplicitTi port for STM32 (latest version http://x89300.codeplex.com/ )☆11Feb 15, 2014Updated 11 years ago
- A mini development environment for developing and troubleshooting the Cypress PSoC Digital Filter Block☆11Mar 23, 2020Updated 5 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆40Jun 19, 2024Updated last year
- OrangePi_CedarX☆35Mar 7, 2017Updated 8 years ago
- Fly your planes to victory as you re-create the aerial battles of the First World War!☆12Oct 24, 2025Updated 3 months ago
- A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance☆16Aug 24, 2024Updated last year
- CKLink_Lite☆11Oct 18, 2021Updated 4 years ago
- Graphical Effects for Qt, with original features but for Qt6☆10Apr 2, 2022Updated 3 years ago
- Rust support for RISC-V Platform-Level Interrupt Controller☆10Oct 13, 2022Updated 3 years ago
- USB accessory with pyusb☆15Mar 31, 2014Updated 11 years ago
- 这是为ESP32 micropython 开发的一款通过wifi进行热更新代码的工具,旨在为各位MicroPython爱好者带来更好的开发体验和开发效率.☆13Nov 26, 2018Updated 7 years ago
- ☆14May 15, 2021Updated 4 years ago
- Source of Feitian OpenSK USB Dongle help docs.☆12Jul 5, 2022Updated 3 years ago