sipeed / TangMega-138KPro-example
Tang Mega 138K Pro examples
☆68Updated 4 months ago
Alternatives and similar repositories for TangMega-138KPro-example:
Users that are interested in TangMega-138KPro-example are comparing it to the libraries listed below
- Basic USB 1.1 Host Controller for small FPGAs☆89Updated 4 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆76Updated last year
- DisplayPort IP-core☆62Updated last week
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆265Updated 3 months ago
- TangMega-138K-example project☆32Updated 3 weeks ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆54Updated last year
- TangNano-20K-example☆114Updated last year
- FPGA Logic Analyzer and GUI☆124Updated 2 years ago
- An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA☆74Updated 2 years ago
- TangPrimer-20K-example project☆194Updated 6 months ago
- A compact USB HID host FPGA core supporting keyboards, mice and gamepads.☆120Updated 3 weeks ago
- Opensource DDR3 Controller☆310Updated 3 weeks ago
- iCESugar series FPGA dev board☆172Updated 9 months ago
- Minimal DVI / HDMI Framebuffer☆79Updated 4 years ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆166Updated last year
- 8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.☆171Updated 5 years ago
- Tiny tips for Colorlight i5 FPGA board☆57Updated 4 years ago
- Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)☆133Updated last year
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated 11 months ago
- Open-source high performance AXI4-based HyperRAM memory controller☆73Updated 2 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆94Updated 4 years ago
- 国产VU13P加速卡资料☆70Updated last month
- USB3 PIPE interface for Xilinx 7-Series☆211Updated 2 years ago
- Basic USB-CDC device core (Verilog)☆76Updated 3 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆52Updated 9 months ago
- Microsoft Catapult FPGA, Catapult V3, PCIE Test Demo, On-board usb Blaster and OpenCL BSP☆54Updated 2 years ago
- Small (Q)SPI flash memory programmer in Verilog☆61Updated 2 years ago
- Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.☆136Updated 3 years ago
- A full-speed device-side USB peripheral core written in Verilog.☆230Updated 2 years ago
- AGM bitstream utilities and decoded files from Supra☆42Updated last year