Alternatives and similar repositories for security:

Users that are interested in security are comparing it to the libraries listed below

• riscv-admin / iopmp
  Group administration repository for Tech: IOPMP Task Group
  ☆13Updated 2 months ago
• riscv-admin / trusted-computing
  ☆22Updated last year
• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆20Updated this week
• riscv-non-isa / riscv-ap-tee
  This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the …
  ☆52Updated last month
• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆29Updated 6 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆22Updated 4 months ago
• vusec / tlbdr
  ☆18Updated 2 years ago
• riscv / riscv-spmp
  The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by…
  ☆12Updated 5 months ago
• gururaj-s / mirage
  MIRAGE (USENIX Security 2021)
  ☆12Updated last year
• CSL-KU / SpectreGuard
  Data-centric defense mechanism against Spectre attacks. (DAC'19)
  ☆11Updated 5 years ago
• sectrs-acai / acai
  Protecting Accelerator Execution with Arm Confidential Computing Architecture (USENIX Security 2024)
  ☆26Updated last year
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆43Updated this week
• riscv-admin / uarch-side-channels
  ☆15Updated 2 months ago
• gururaj-s / cleanupspec
  CleanupSpec (MICRO-2019)
  ☆17Updated 4 years ago
• efeslab / dolma
  ☆12Updated 4 years ago
• riscvarchive / riscv-tee
  ☆38Updated 2 years ago
• TwinVisor / twinvisor-prototype
  ☆21Updated 2 years ago
• Penglai-Enclave / Penglai-Enclave
  This is the main repo for Penglai.
  ☆68Updated last year
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆11Updated 3 years ago
• zero-day-labs / riscv-iommu-demo
  RISC-V IOMMU Demo (Linux & Bao)
  ☆17Updated last year
• gururaj-s / streamline
  Streamline Covert Channel Attack (presented in ASPLOS'21)
  ☆19Updated 4 years ago
• compsec-snu / specdoctor
  ☆22Updated last year
• hku-systems / cronus
  ☆16Updated 2 years ago
• dskarlatos / MicroScope
  Microscope: Enabling Microarchitectural Replay Attacks
  ☆18Updated 4 years ago
• ilebedev / sanctum
  The MIT Sanctum processor top-level project
  ☆28Updated 4 years ago
• cwfletcher / oisa
  Data oblivious ISA prototyped on the RISC-V BOOM processor.
  ☆20Updated 2 years ago
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆58Updated 6 months ago
• michaeljclark / rv8-bench
  rv8 benchmark suite
  ☆18Updated 4 years ago
• mjyan0720 / InvisiSpec-1.0
  Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.
  ☆59Updated 4 years ago
• sslab-gatech / SNAP
  ☆13Updated 3 years ago