Alternatives and similar repositories for prospect

Users that are interested in prospect are comparing it to the libraries listed below

• riscv-admin / iopmp
  Group administration repository for Tech: IOPMP Task Group
  ☆13Updated last year
• riscv-admin / trusted-computing
  ☆23Updated 2 years ago
• cwfletcher / oisa
  Data oblivious ISA prototyped on the RISC-V BOOM processor.
  ☆23Updated 3 years ago
• dskarlatos / MicroScope
  Microscope: Enabling Microarchitectural Replay Attacks
  ☆20Updated 5 years ago
• ilebedev / sanctum
  The MIT Sanctum processor top-level project
  ☆31Updated 5 years ago
• gururaj-s / mirage
  MIRAGE (USENIX Security 2021)
  ☆14Updated 2 years ago
• riscv-non-isa / riscv-ap-tee
  This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the …
  ☆65Updated last month
• rivosinc / salus
  Risc-V hypervisor for TEE development
  ☆126Updated 3 weeks ago
• gururaj-s / streamline
  Streamline Covert Channel Attack (presented in ASPLOS'21)
  ☆22Updated 4 years ago
• riscvarchive / security
  RISC-V Security HC admin repo
  ☆18Updated last year
• mjyan0720 / InvisiSpec-1.0
  Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.
  ☆61Updated 5 years ago
• cwfletcher / stt
  ☆34Updated last month
• pwnall / sanctum
  Minimal RISC Extensions for Isolated Execution
  ☆54Updated 6 years ago
• gururaj-s / cleanupspec
  CleanupSpec (MICRO-2019)
  ☆16Updated 5 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆28Updated 7 months ago
• jasonyu1996 / elasticlave
  ☆28Updated 11 months ago
• KULeuven-COSIC / ShowTime
  Artifacts for our ShowTime paper (AsiaCCS '23), including distinguishing cache hits and misses with the human eye.
  ☆14Updated 2 years ago
• FxPiGaAo / Hacky-Racer
  ☆17Updated 7 months ago
• cgvwzq / cachequery
  HW interface for memory caches
  ☆28Updated 5 years ago
• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆21Updated 4 months ago
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆17Updated 4 years ago
• riscv-boom / boom-attacks
  Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)
  ☆68Updated 6 years ago
• MATCHA-MIT / Pensieve
  This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.
  ☆24Updated 2 years ago
• efeslab / dolma
  ☆14Updated 4 years ago
• FPSG-UIUC / Peek-a-Walk
  Proof-of-concept code for the IEEE S&P 2025 paper "Peek-a-Walk: Leaking Secrets via Page Walk Side Channels"
  ☆31Updated 7 months ago
• riscv / riscv-spmp
  The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by…
  ☆21Updated 2 months ago
• larkmjc / rv8-bench
  rv8 benchmark suite
  ☆23Updated 5 years ago
• KULeuven-COSIC / PRIME-SCOPE
  The open-source component of Prime+Scope, published at CCS 2021
  ☆36Updated 2 years ago
• Penglai-Enclave / Penglai-Enclave-TVM
  The main repo of Penglai Enclave based on RISC-V Trapped Virtual Memory (TVM).
  ☆41Updated 2 years ago
• flowyroll / uarchsec
  ☆48Updated 7 years ago