Alternatives and similar repositories for prospect

Users that are interested in prospect are comparing it to the libraries listed below

• riscv-admin / iopmp
  Group administration repository for Tech: IOPMP Task Group
  ☆13Updated 11 months ago
• ilebedev / sanctum
  The MIT Sanctum processor top-level project
  ☆31Updated 5 years ago
• rivosinc / salus
  Risc-V hypervisor for TEE development
  ☆125Updated 5 months ago
• riscv-non-isa / riscv-ap-tee
  This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the …
  ☆64Updated 6 months ago
• cwfletcher / oisa
  Data oblivious ISA prototyped on the RISC-V BOOM processor.
  ☆23Updated 3 years ago
• riscv-admin / trusted-computing
  ☆23Updated 2 years ago
• riscv / riscv-spmp
  The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by…
  ☆21Updated last week
• pwnall / sanctum
  Minimal RISC Extensions for Isolated Execution
  ☆54Updated 6 years ago
• riscvarchive / security
  RISC-V Security HC admin repo
  ☆18Updated 10 months ago
• hex-five / multizone-sdk
  MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn'…
  ☆86Updated last year
• riscv-boom / boom-attacks
  Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)
  ☆67Updated 6 years ago
• Penglai-Enclave / Penglai-Enclave-TVM
  The main repo of Penglai Enclave based on RISC-V Trapped Virtual Memory (TVM).
  ☆41Updated 2 years ago
• riscvarchive / riscv-tee
  ☆38Updated 3 years ago
• dskarlatos / MicroScope
  Microscope: Enabling Microarchitectural Replay Attacks
  ☆20Updated 5 years ago
• crosscon / CROSSCON-Hypervisor
  CROSSCON-Hypervisor, a Lightweight Hypervisor
  ☆20Updated last month
• gururaj-s / cleanupspec
  CleanupSpec (MICRO-2019)
  ☆16Updated 5 years ago
• sslab-gatech / open-tdx
  ☆42Updated last month
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆17Updated 4 years ago
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆64Updated this week
• keystone-enclave / keystone-demo
  Demo host and enclave applications exercising most functionality.
  ☆31Updated 2 years ago
• ccc-spdm-tools / spdm-rs
  A rust implementation for DMTF SPDM protocol to support Confidential Computing
  ☆47Updated last week
• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆29Updated 7 years ago
• gururaj-s / mirage
  MIRAGE (USENIX Security 2021)
  ☆14Updated 2 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆27Updated 5 months ago
• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆21Updated 2 months ago
• TF-RMM / tf-rmm
  Reference implementation of Arm-CCA RMM specification
  ☆66Updated this week
• riscv / riscv-cfi
  This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …
  ☆92Updated this week
• ESCristiano / BUSted
  BUSted!!! Microarchitectural Side-Channel Attacks on the MCU Bus Interconnect
  ☆11Updated last year
• comsec-group / cascade-artifacts
  Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)
  ☆137Updated last year
• islet-project / islet
  An on-device confidential computing platform
  ☆131Updated this week