proteus-core / prospectLinks
ProSpeCT: Provably Secure Speculation for the Constant-Time Policy.
☆19Updated 5 months ago
Alternatives and similar repositories for prospect
Users that are interested in prospect are comparing it to the libraries listed below
Sorting:
- Group administration repository for Tech: IOPMP Task Group☆13Updated last year
- This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the …☆65Updated last month
- ☆23Updated 2 years ago
- The MIT Sanctum processor top-level project☆31Updated 5 years ago
- Data oblivious ISA prototyped on the RISC-V BOOM processor.☆23Updated 3 years ago
- Risc-V hypervisor for TEE development☆126Updated 3 weeks ago
- Microscope: Enabling Microarchitectural Replay Attacks☆20Updated 5 years ago
- Artifacts for our ShowTime paper (AsiaCCS '23), including distinguishing cache hits and misses with the human eye.☆14Updated 2 years ago
- The main repo of Penglai Enclave based on RISC-V Trapped Virtual Memory (TVM).☆41Updated 2 years ago
- The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by…☆21Updated 2 months ago
- Minimal RISC Extensions for Isolated Execution☆54Updated 6 years ago
- An on-device confidential computing platform☆134Updated last month
- RISC-V Security HC admin repo☆18Updated last year
- ☆28Updated 11 months ago
- ☆34Updated last month
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆61Updated 5 years ago
- ☆38Updated 3 years ago
- Proof-of-concept code for the IEEE S&P 2025 paper "Peek-a-Walk: Leaking Secrets via Page Walk Side Channels"☆31Updated 7 months ago
- Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly☆17Updated 4 years ago
- ☆48Updated 7 years ago
- ☆119Updated 3 years ago
- This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …☆95Updated this week
- Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser☆62Updated 3 years ago
- ☆43Updated 3 months ago
- This repository contains source code and experimental data of multiple cache side-channel attacks on Intel x86 architecture.☆57Updated 6 years ago
- This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.☆24Updated 2 years ago
- RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)☆23Updated 6 years ago
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆68Updated 6 years ago
- A flush-reload side channel attack implementation☆56Updated 3 years ago
- Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)☆138Updated last year