Alternatives and similar repositories for prospect:

Users that are interested in prospect are comparing it to the libraries listed below

• dskarlatos / MicroScope
  Microscope: Enabling Microarchitectural Replay Attacks
  ☆19Updated 4 years ago
• riscv-admin / iopmp
  Group administration repository for Tech: IOPMP Task Group
  ☆13Updated 4 months ago
• cwfletcher / oisa
  Data oblivious ISA prototyped on the RISC-V BOOM processor.
  ☆21Updated 2 years ago
• cispa / mwait
  Proof-of-concept implementation for the paper "(M)WAIT for It: Bridging the Gap between Microarchitectural and Architectural Side Channel…
  ☆25Updated last year
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆15Updated 3 years ago
• MATCHA-MIT / Pensieve
  This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.
  ☆23Updated last year
• libtea / frameworks
  Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser
  ☆61Updated 2 years ago
• gururaj-s / mirage
  MIRAGE (USENIX Security 2021)
  ☆12Updated last year
• scy-phy / plumber
  Code for the CCS 2022 paper "Microarchitectural Leakage Templates and Their Application to Cache-Based Side Channels".
  ☆13Updated 2 years ago
• cgvwzq / cachequery
  HW interface for memory caches
  ☆26Updated 5 years ago
• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆29Updated 6 years ago
• ilebedev / sanctum
  The MIT Sanctum processor top-level project
  ☆28Updated 5 years ago
• riscv-admin / trusted-computing
  ☆22Updated last year
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆65Updated last month
• riscv-admin / security
  RISC-V Security HC admin repo
  ☆17Updated 3 months ago
• ARM-software / cca-rmm-acs
  Tests for verifying compliance of RMM implementations
  ☆18Updated last month
• gururaj-s / streamline
  Streamline Covert Channel Attack (presented in ASPLOS'21)
  ☆20Updated 4 years ago
• ahoi-attacks / WeSee
  Using Malicious #VC Interrupts to Break AMD SEV-SNP (IEEE S&P 2024)
  ☆24Updated last year
• KULeuven-COSIC / ShowTime
  Artifacts for our ShowTime paper (AsiaCCS '23), including distinguishing cache hits and misses with the human eye.
  ☆12Updated last year
• ibm-research / speculator
  Tool to Analyze Speculative Execution Attacks and Mitigations
  ☆55Updated 3 years ago
• riscv-non-isa / riscv-ap-tee
  This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the …
  ☆55Updated last month
• flowyroll / medusa
  Medusa Repository: Transynther tool and Medusa Attack
  ☆21Updated 4 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆24Updated 7 months ago
• nagnagnet / PrimeProbe
  ☆18Updated 6 years ago
• vernamlab / medusa
  Medusa Repository: Transynther tool and Medusa Attack
  ☆20Updated 4 years ago
• compsec-snu / specdoctor
  ☆24Updated 2 years ago
• vusec / tlbdr
  ☆17Updated 2 years ago
• rzhang2285 / Coppelia
  Code repository for Coppelia tool
  ☆23Updated 4 years ago
• FPSG-UIUC / Pandora
  Opening Pandora's Box: A Systematic Study of New Ways Microarchitecture can Leak Private Data
  ☆20Updated 2 years ago
• jasonyu1996 / elasticlave
  ☆23Updated last month