Alternatives and similar repositories for nand2tetris

Users that are interested in nand2tetris are comparing it to the libraries listed below

• ejrh / cpu
  A very primitive but hopefully self-educational CPU in Verilog
  ☆144Updated 10 years ago
• twilco / riscv-from-scratch
  The code for the RISC-V from scratch blog post series.
  ☆90Updated 4 years ago
• kvakil / venus
  RISC-V instruction set simulator built for education
  ☆203Updated 3 years ago
• mathis-s / SoomRV
  A simple superscalar out-of-order RISC-V microprocessor
  ☆205Updated 3 months ago
• lowenware / leos-kernel
  LeOS operating system Kernel for AArch64 written in Rust
  ☆80Updated 4 years ago
• merledu / nucleusrv
  NucleusRV - A 32-bit 5 staged pipelined risc-v core.
  ☆66Updated last month
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆268Updated this week
• RobertBaruch / riscv-reboot
  ☆41Updated 4 years ago
• nbdd0121 / muntjac-soc
  SoC for muntjac
  ☆12Updated last month
• rafaelcalcada / rvx
  RISC-V microcontroller IP core developed in Verilog
  ☆173Updated last month
• leos313 / ldd3_training
  Examples for learning how to write linux device drivers following ldd3
  ☆37Updated 5 years ago
• moratorium08 / osmium
  A toy operating system written in Rust on RISC V(rv32im)
  ☆204Updated 2 years ago
• riscv / riscv-cheri
  This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…
  ☆68Updated 2 weeks ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆146Updated 7 months ago
• bao-project / bao-helloworld
  ☆10Updated 3 months ago
• sysprog21 / semu
  A minimalist RISC-V system emulator capable of running Linux kernel
  ☆260Updated this week
• rdiez / uart_dpi
  DPI module for UART-based console interaction with Verilator simulations
  ☆23Updated 12 years ago
• mkilgore / protura
  ☆90Updated 3 years ago
• riscvarchive / risc-v-getting-started-guide
  The official RISC-V getting started guide
  ☆200Updated last year
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆238Updated 7 months ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆158Updated this week
• kuopinghsu / srv32
  Simple 3-stage pipeline RISC-V processor
  ☆139Updated last year
• RoaLogic / RV12
  RISC-V CPU Core
  ☆327Updated 11 months ago
• riscvarchive / educational-materials
  Educational materials for RISC-V
  ☆223Updated 4 years ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆669Updated last week
• digital-design-hq / Digital-Resources
  ☆59Updated 3 years ago
• DavidSpickett / BadgerKernel
  Multitasking kernel for Arm/Thumb/AArch64 targets.
  ☆49Updated 3 years ago
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆165Updated 4 years ago
• Chalk-OS / tabfs-specs
  Specifications for the tabfs filesystem (osdev) | Mirror of https://codearq.net/chalk-os/tabfs-specs
  ☆16Updated 11 months ago
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆368Updated last year