jeremycw / tetris-verilog

Related projects ⓘ

Alternatives and complementary repositories for tetris-verilog

• polysome / evolvable_motherboard
  Paul Layzell's Evolvable Motherboard
  ☆12Updated 9 years ago
• Gladdy / numerical-fpga-thesis
  Bachelor thesis Martijn Bakker -- Numerical mathematics on FPGAs using CλaSH
  ☆28Updated 9 years ago
• mangpo / chlorophyll
  Synthesis-Aided Compiler for GreenArrays GA144
  ☆51Updated 7 years ago
• Lichtso / UnikernelExperiments
  TCP/IPv6-enabled Pine64+ bootloader
  ☆13Updated 7 years ago
• azonenberg / antikernel
  The Antikernel operating system project
  ☆113Updated 4 years ago
• BookOwl / scratching-forth
  A compiler from Forth to Scratch
  ☆21Updated 8 years ago
• aidanhs / schrotcl
  Schrödinger's Tcl
  ☆30Updated 9 years ago
• libresilicon / process
  ☆87Updated 5 years ago
• riscvarchive / ISA_Formal_Spec_Public_Review
  Locus site for Public Review of Several RISC-V ISA Formal Specs
  ☆73Updated 4 years ago
• combinatorylogic / soc
  An experimental System-on-Chip with a custom compiler toolchain.
  ☆59Updated 4 years ago
• leviathanch / qtflow
  A Qt5 based free VLSI development tool
  ☆30Updated 6 years ago
• JohnDRO / Golirev-IDE
  An online Verilog IDE based on YosysJS.
  ☆24Updated 8 years ago
• GreatAttractor / libskry_r
  Lucky imaging library
  ☆17Updated 4 years ago
• KevinMGranger / nine
  The 9p protocol as a serde format and message types.
  ☆30Updated 3 years ago
• NuxiNL / flower
  Label-based networking daemon
  ☆22Updated 5 years ago
• IonoclastBrigham / firth
  A simple Forth-like language intended for DSL creation, implemented in Lua.
  ☆26Updated 2 years ago
• solbjorg / oberon-riscv
  Oberon RISC-V port, based on Samuel Falvo's RISC-V compiler and Peter de Wachter's Project Norebo. Part of an academic project to evaluat…
  ☆75Updated 3 years ago
• Poofjunior / fpga_fast_serial_sort
  a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
  ☆37Updated 8 years ago
• alehander92 / hatlog
  custom type systems for python in prolog: http://alehander42.me/prolog_type_systems
  ☆24Updated 8 years ago
• rongarret / clmm
  An exercise in cryptographic minimlism
  ☆24Updated 9 years ago
• stephenrkell / donald
  The Mickey Mouse of dynamic linkers
  ☆14Updated last week
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆46Updated 7 years ago
• ujamjar / hardcaml
  [Deprecated see github.com/janestreet/hardcaml] Register Transfer Level Hardware Design in OCaml
  ☆119Updated 3 years ago
• cbiffle / cfm
  A 16-bit CPU and self-hosting Forth system for the Lattice ICE40 FPGA, written in Haskell.
  ☆47Updated 3 years ago
• libresilicon / PearlRiver
  1st Testwafer for LibreSilicon
  ☆28Updated 5 years ago
• diamondman / Adapt
  The client library for ProteusISC
  ☆26Updated 6 years ago
• alfanick / xxcalc-rs
  Embeddable or standalone robust floating-point polynomial calculator written in Rust.
  ☆13Updated 7 years ago
• stephank / rvsim
  A RISC-V simulator implementing RV32G[C].
  ☆34Updated last year
• drom / quark
  Stack CPU Work In Progress
  ☆30Updated 10 months ago
• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆54Updated 5 years ago