Alternatives and similar repositories for tetris-verilog

Users that are interested in tetris-verilog are comparing it to the libraries listed below

• combinatorylogic / soc
  An experimental System-on-Chip with a custom compiler toolchain.
  ☆60Updated 5 years ago
• andportnoy / riscv-disassembler
  A minimal RISC-V RV32I disassembler
  ☆56Updated 4 years ago
• nickmqb / wyre
  Hardware definition language that compiles to Verilog
  ☆106Updated 4 years ago
• azonenberg / antikernel
  The Antikernel operating system project
  ☆119Updated 5 years ago
• mangpo / chlorophyll
  Synthesis-Aided Compiler for GreenArrays GA144
  ☆54Updated 8 years ago
• pwmarcz / fpga-chip8
  CHIP-8 console on FPGA
  ☆199Updated 6 years ago
• zhemao / ez8
  The Easy 8-bit Processor
  ☆183Updated 11 years ago
• mrisc32 / mrisc32
  MRSIC32 ISA documentation and development
  ☆91Updated 2 years ago
• KestrelComputer / kestrel
  The Kestrel is a family of home-made computers, built as much as possible on open-source technology, and supporting as much as possible t…
  ☆188Updated 4 years ago
• drom / quark
  Stack CPU Work In Progress
  ☆30Updated last year
• libresilicon / process
  ☆91Updated 6 years ago
• cbiffle / cfm
  A 16-bit CPU and self-hosting Forth system for the Lattice ICE40 FPGA, written in Haskell.
  ☆59Updated 4 years ago
• leviathanch / qtflow
  A Qt5 based free VLSI development tool
  ☆31Updated 7 years ago
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆53Updated 4 years ago
• howerj / forth-cpu
  A Forth CPU and System on a Chip, based on the J1, written in VHDL
  ☆361Updated last year
• inforichland / freezing-spice
  A pipelined RISCV implementation in VHDL
  ☆96Updated 6 years ago
• howerj / bit-serial
  A bit-serial CPU written in VHDL, with a simulator written in C.
  ☆130Updated last year
• solbjorg / oberon-riscv
  Oberon RISC-V port, based on Samuel Falvo's RISC-V compiler and Peter de Wachter's Project Norebo. Part of an academic project to evaluat…
  ☆77Updated 4 years ago
• dawsonjon / Chips-2.0
  FPGA Design Suite based on C to Verilog design flow.
  ☆246Updated 6 years ago
• polysome / aggregate-1
  An open source miniPCIe development board based on the Xilinx Spartan 6 LX150T
  ☆145Updated 9 years ago
• jamesbowman / swapforth
  Swapforth is a cross-platform ANS Forth
  ☆295Updated last year
• jamesbowman / j1
  The J1 CPU
  ☆171Updated 5 years ago
• brouhaha / glacial
  Glacial - microcoded RISC-V core designed for low FPGA resource utilization
  ☆86Updated 5 years ago
• Lichtso / UnikernelExperiments
  TCP/IPv6-enabled Pine64+ bootloader
  ☆13Updated 8 years ago
• JohnDRO / Golirev-IDE
  An online Verilog IDE based on YosysJS.
  ☆24Updated 9 years ago
• revaldinho / opc
  One Page CPU Project - CPU, Assembler & Emulator each in a single page of code
  ☆82Updated last year
• cseed / cynth
  a simple C-to-Verilog compiler
  ☆51Updated 8 years ago
• jjyr / jonesforth_riscv
  Jonesforth RISC-V port.
  ☆61Updated 4 years ago
• fabioperez / space-invaders-vhdl
  Space Invaders game implemented with VHDL
  ☆156Updated 9 years ago
• diamondman / Adapt
  The client library for ProteusISC
  ☆26Updated 7 years ago