jeremycw / tetris-verilog
Verilog Tetris
☆13Updated 10 years ago
Alternatives and similar repositories for tetris-verilog:
Users that are interested in tetris-verilog are comparing it to the libraries listed below
- Synthesis-Aided Compiler for GreenArrays GA144☆52Updated 8 years ago
- TCP/IPv6-enabled Pine64+ bootloader☆13Updated 7 years ago
- An experimental System-on-Chip with a custom compiler toolchain.☆59Updated 5 years ago
- Bachelor thesis Martijn Bakker -- Numerical mathematics on FPGAs using CλaSH☆28Updated 9 years ago
- A compiler from Forth to Scratch☆22Updated 8 years ago
- The Antikernel operating system project☆115Updated 4 years ago
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆53Updated 3 years ago
- Stack CPU Work In Progress☆30Updated last year
- Unsorted Playground for Machine Learning, Reinforcement Learning and other AI Experiments☆14Updated 2 years ago
- JIT compiler for 6502 machine code, built on lib6502 and LLVM☆54Updated 10 years ago
- An exercise in cryptographic minimlism☆24Updated 9 years ago
- A single instruction set processor architecture☆18Updated 7 years ago
- MRSIC32 ISA documentation and development☆90Updated last year
- Oberon RISC-V port, based on Samuel Falvo's RISC-V compiler and Peter de Wachter's Project Norebo. Part of an academic project to evaluat…☆76Updated 4 years ago
- Schrödinger's Tcl☆30Updated 9 years ago
- A bit-serial CPU written in VHDL, with a simulator written in C.☆123Updated 4 months ago
- A minimal RISC-V RV32I disassembler☆55Updated 3 years ago
- Bootstrap compiler☆44Updated 5 years ago
- A 16-bit CPU and self-hosting Forth system for the Lattice ICE40 FPGA, written in Haskell.☆49Updated 3 years ago
- The Mickey Mouse of dynamic linkers☆14Updated last month
- Hardware definition language that compiles to Verilog☆106Updated 3 years ago
- ☆89Updated 5 years ago
- A simple Forth-like language intended for DSL creation, implemented in Lua.☆27Updated 2 years ago
- a simple C-to-Verilog compiler☆48Updated 7 years ago
- A re-implementation of ShapeCPU☆18Updated 2 years ago
- IEEE754 reduced reduced precision floating point☆22Updated 7 years ago
- A Qt5 based free VLSI development tool☆30Updated 6 years ago
- QWERTY handset with wifi module and epaper display☆16Updated 7 years ago
- An online Verilog IDE based on YosysJS.☆24Updated 9 years ago