pabennett / uartLinks
A VHDL UART for communicating over a serial link with an FPGA
☆74Updated 9 years ago
Alternatives and similar repositories for uart
Users that are interested in uart are comparing it to the libraries listed below
Sorting:
- Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL☆172Updated last year
- Library of VHDL components that are useful in larger designs.☆235Updated last year
- Source code from the MicroZed Chronicles blog hosted by Xcell Daily Blog☆194Updated 6 years ago
- Collection of open-source peripherals in Verilog☆179Updated 3 years ago
- (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…☆89Updated 6 years ago
- Simple UART controller for FPGA written in VHDL☆99Updated 3 years ago
- Verilog wishbone components☆115Updated last year
- Flexible VHDL library☆187Updated 2 years ago
- SPI master and SPI slave for FPGA written in VHDL☆176Updated 4 years ago
- Migrated to Codeberg☆92Updated 8 years ago
- ☆63Updated 8 years ago
- Examples using the Cyclone V SoC chip☆106Updated 6 years ago
- ☆113Updated 3 months ago
- Verilog modules required to get the OV7670 camera working☆72Updated 6 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 5 years ago
- Verilog digital signal processing components☆144Updated 2 years ago
- ☆86Updated 8 years ago
- A collection of demonstration digital filters☆154Updated last year
- Xilinx Virtual Cable Server for Raspberry Pi☆115Updated 3 years ago
- A testbench for an axi lite custom IP☆23Updated 10 years ago
- Example design for the Ethernet FMC using the hard GEMs of the Zynq☆57Updated 2 months ago
- This is a wiki and code sharing for ZYNQ☆73Updated 9 years ago
- Simple C snippet to transfer DMA memory with scatter/gather on a Zynq 7020☆54Updated 8 years ago
- FuseSoC standard core library☆144Updated last month
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆96Updated 3 years ago
- SPI Master for FPGA - VHDL and Verilog☆296Updated last year
- DPLL for phase-locking to 1PPS signal☆32Updated 8 years ago
- A simple, basic, formally verified UART controller☆307Updated last year
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 7 years ago
- Demonstration of the AXI DMA engine on the MicroZed☆26Updated 4 years ago