Alternatives and similar repositories for uart:

Users that are interested in uart are comparing it to the libraries listed below

• jakubcabal / spi-fpga
  SPI master and SPI slave for FPGA written in VHDL
  ☆168Updated 3 years ago
• analogdevicesinc / fpgahdl_xilinx
  (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…
  ☆88Updated 6 years ago
• yol / ethernet_mac
  Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL
  ☆157Updated 11 months ago
• oetr / FPGA-I2C-Minion
  A simple I2C minion in VHDL
  ☆60Updated 5 years ago
• xesscorp / VHDL_Lib
  Library of VHDL components that are useful in larger designs.
  ☆229Updated last year
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆182Updated last year
• nandland / spi-master
  SPI Master for FPGA - VHDL and Verilog
  ☆267Updated last year
• q3k / zturn-stuff
  Various files for the MYiR ZTurn Zynq 7010 board
  ☆87Updated 7 years ago
• nandland / spi-slave
  SPI Slave for FPGA in Verilog and VHDL
  ☆191Updated 8 months ago
• ATaylorCEngFIET / MicroZed-Chronicles
  Source code from the MicroZed Chronicles blog hosted by Xcell Daily Blog
  ☆188Updated 6 years ago
• jakubcabal / uart-for-fpga
  Simple UART controller for FPGA written in VHDL
  ☆92Updated 3 years ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆131Updated this week
• frobino / axi_custom_ip_tb
  A testbench for an axi lite custom IP
  ☆22Updated 10 years ago
• imrickysu / ZYNQ-Cookbook
  This is a wiki and code sharing for ZYNQ
  ☆71Updated 8 years ago
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆221Updated 7 months ago
• jamieiles / uart
  Verilog UART
  ☆133Updated 11 years ago
• FMCHUB / Lib_Altium
  Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard
  ☆42Updated 3 years ago
• CospanDesign / nysa-sata
  ☆82Updated 7 years ago
• Digilent / ZYBO
  ☆61Updated 7 years ago
• robertofem / CycloneVSoC-examples
  Examples using the Cyclone V SoC chip
  ☆106Updated 5 years ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆94Updated 2 years ago
• imrickysu / ZYNQ-Custom-Board-Bring-Up-Guide
  This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…
  ☆64Updated 7 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆113Updated last year
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆141Updated last year
• derekmulcahy / xvcpi
  Xilinx Virtual Cable Server for Raspberry Pi
  ☆110Updated 2 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 6 years ago
• fpgadeveloper / ethernet-fmc-zynq-gem
  Example design for the Ethernet FMC using the hard GEMs of the Zynq
  ☆54Updated last month
• klyone / opencores-ip
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆62Updated 9 years ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆66Updated 3 weeks ago
• Digilent / digilent-vivado-scripts
  ☆64Updated 6 months ago