Alternatives and similar repositories for vm80a:

Users that are interested in vm80a are comparing it to the libraries listed below

• 1801BM1 / cpu11
  Revengineered ancient PDP-11 CPUs, originals and clones
  ☆159Updated this week
• AndresNavarro82 / vt52-fpga
  ☆96Updated 3 years ago
• howerj / bit-serial
  A bit-serial CPU written in VHDL, with a simulator written in C.
  ☆124Updated 8 months ago
• gdevic / Z80Explorer
  Visual Zilog Z80 netlist-level simulator
  ☆160Updated last week
• Arlet / verilog-65C02-microcode
  65C02 microprocessor in verilog, small size,reduced cycle count, asynchronous interface
  ☆73Updated 2 years ago
• tomverbeure / panologic-g2
  Pano Logic G2 Reverse Engineering Project
  ☆140Updated 3 years ago
• brouhaha / glacial
  Glacial - microcoded RISC-V core designed for low FPGA resource utilization
  ☆84Updated 5 years ago
• hrvach / fpg1
  FPGA implementation of DEC PDP-1 computer (1959) in Verilog, with CRT, Teletype and Console.
  ☆190Updated 2 years ago
• zylin / zpu
  The Zylin ZPU
  ☆243Updated 10 years ago
• alangarf / apple-one
  An attempt at a small Verilog implementation of the original Apple 1 on an FPGA
  ☆140Updated last year
• wfjm / w11
  PDP-11/70 CPU core and SoC
  ☆123Updated 10 months ago
• archlabo / Frix
  IBM PC Compatible SoC for a commercially available FPGA board
  ☆70Updated 8 years ago
• nullobject / sdram-fpga
  A FPGA core for a simple SDRAM controller.
  ☆118Updated 3 years ago
• zf3 / neoapple2
  Port of Stephen A. Edwards's Apple2fpga to PYNQ-Z1 (Xilinx Zynq FPGA), to emulate an Apple II+.
  ☆44Updated 3 years ago
• jamieiles / 80x86
  80186 compatible SystemVerilog CPU core and FPGA reference design
  ☆395Updated last year
• gdevic / A-Z80
  An implementation of the Z80 CPU for Altera, Xilinx and Lattice FPGAs
  ☆155Updated 4 years ago
• turbo9team / turbo9
  Turbo9 - Pipelined 6809 Microprocessor IP
  ☆156Updated 7 months ago
• shirriff / xc2064
  Reverse engineering the XC2064 FPGA
  ☆74Updated 3 years ago
• skiphansen / pano_z80
  Retro Z80 computer for the Pano Logic Thin Client
  ☆46Updated 3 years ago
• howerj / forth-cpu
  A Forth CPU and System on a Chip, based on the J1, written in VHDL
  ☆344Updated last year
• MEGA65 / mega65-core
  MEGA65 FPGA core
  ☆262Updated last week
• tomverbeure / panologic
  PanoLogic Zero Client G1 reverse engineering info
  ☆74Updated last year
• 74hc595 / 68k-nano
  Minimal 68000-based single board computer
  ☆291Updated 4 years ago
• TimRudy / ice-chips-verilog
  IceChips is a library of all common discrete logic devices in Verilog
  ☆141Updated 5 months ago
• DegateCommunity / Degate
  A modern and open-source cross-platform software for chips reverse engineering.
  ☆259Updated 5 months ago
• RobertBaruch / riscv-reboot
  ☆41Updated 4 years ago
• pwmarcz / fpga-chip8
  CHIP-8 console on FPGA
  ☆193Updated 6 years ago
• RobertBaruch / lmarv
  Building a RISC-V processor out of LSI logic
  ☆90Updated 4 years ago
• grahamedgecombe / icicle
  32-bit RISC-V system on chip for iCE40 FPGAs
  ☆305Updated last year
• smunaut / ice40-playground
  Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)
  ☆252Updated last year