lucasbrasilino / axis_exec_opLinks
Verilog module for executing logic operations over AXI4-Stream interface data.
☆10Updated 3 years ago
Alternatives and similar repositories for axis_exec_op
Users that are interested in axis_exec_op are comparing it to the libraries listed below
Sorting:
- FPGA and Digital ASIC Build System☆74Updated 2 weeks ago
- ☆28Updated 3 years ago
- VHDL-2008 Support Library☆57Updated 8 years ago
- ☆94Updated last year
- Vivado build system☆69Updated 6 months ago
- This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…☆69Updated 7 years ago
- Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.☆67Updated 4 months ago
- Extensible FPGA control platform☆62Updated 2 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆33Updated 4 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆70Updated 9 months ago
- OSVVM Documentation☆34Updated this week
- 🤖 SoCFPGA: Open-Source Embedded Linux Distribution with a highly flexible build system, developed for Intel (ALTERA) SoC-FPGAs (Cyclone …☆108Updated 3 years ago
- Control and Status Register map generator for HDL projects☆116Updated last month
- ☆32Updated 2 years ago
- 10G Low Latency Ethernet☆56Updated last year
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆94Updated 5 years ago
- ☆137Updated 2 months ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆171Updated this week
- ☆112Updated 3 months ago
- Python productivity for RFSoC platforms☆76Updated last week
- Ethernet interface modules for Cocotb☆67Updated last year
- tcl scripts used to build or generate vivado projects automatically☆31Updated 2 years ago
- Verilog digital signal processing components☆143Updated 2 years ago
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆79Updated 8 months ago
- bootgen source code☆45Updated last month
- Open-source version of SpaceWire-to-GigabitEther using ZestET1☆23Updated 9 years ago
- An open-source HDL register code generator fast enough to run in real time.☆71Updated last week
- TCL scripts for FPGA (Xilinx)☆32Updated 2 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 4 months ago
- FuseSoC standard core library☆144Updated last month