miscellaneousbits / DE10_NANO_SOC_MINIMAL
SHA3-256 MINER CORE
☆12Updated 4 years ago
Alternatives and similar repositories for DE10_NANO_SOC_MINIMAL:
Users that are interested in DE10_NANO_SOC_MINIMAL are comparing it to the libraries listed below
- SQRL Port of ethminer☆11Updated 4 years ago
- An Open Source FPGA GroestlCoin Miner☆10Updated 7 years ago
- Bitcoin miner for Xilinx FPGAs☆97Updated 11 years ago
- SHA256 in (System-) Verilog / Open Source FPGA Miner☆78Updated 7 years ago
- DE10 NANO SHA3-256 Proof of Work Miner☆13Updated 4 years ago
- Mining CryptoNight Haven on the Varium C1100☆10Updated 3 years ago
- FPGA referrence implementation for aion equihash 2109☆14Updated 6 years ago
- An open source FPGA miner for Blakecoin☆51Updated 10 years ago
- A completely open source implementation of a Bitcoin Miner for Altera FPGAs. This project hopes to promote the free and open development …☆51Updated 11 years ago
- ☆44Updated 3 years ago
- Example verilog / miner for crypto mining using AWS F1 instances☆30Updated 6 years ago
- A SoC for DOOM☆16Updated 3 years ago
- Tool for graphically viewing FPGA bitstream files and their connection to FASM features.☆14Updated 2 years ago
- A simplified version of an FPGA bitcoin miner☆52Updated 5 years ago
- Verilog implementation of the 32-bit version of the Blake2 hash function☆21Updated 2 years ago
- Demo of hdmi on at 720p with VGA-compatible text mode and sound☆26Updated 2 years ago
- PCIe adapter for an FPGA accelerator for Open CloudServer☆23Updated 4 years ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆35Updated last year
- FPGA CryptoNight V7 Minner☆30Updated 5 years ago
- ☆18Updated 4 years ago
- Works in Progress and Experiments for the Innova-2 Flex XCKU15P-based Board☆13Updated 11 months ago
- Open source hardware implementation of classic CryptoNight☆37Updated last year
- RISC-V System on Chip Builder☆12Updated 4 years ago
- A recreation of Williams Defender 1981 arcade game for DE10-Lite FPGA dev board, written in VHDL.☆35Updated 2 years ago
- IP submodules, formatted for easier CI integration☆29Updated last year
- Interface Xilinx XDMA PCIe with DDR3 using MIG-IP on Artix-7 FPGA using Nitefury dev board☆12Updated 2 years ago
- DSP WishBone Compatible Cores☆13Updated 10 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆12Updated 4 years ago
- E300 Development☆10Updated last year
- ☆18Updated 4 years ago