Alternatives and similar repositories for jop:

Users that are interested in jop are comparing it to the libraries listed below

• atgreen / moxie-cores
  Moxie-compatible core repository
  ☆45Updated last year
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆81Updated last year
• jamieiles / oldland-cpu
  Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
  ☆122Updated 8 years ago
• combinatorylogic / soc
  An experimental System-on-Chip with a custom compiler toolchain.
  ☆59Updated 5 years ago
• cseed / cynth
  a simple C-to-Verilog compiler
  ☆48Updated 7 years ago
• archlabo / Frix
  IBM PC Compatible SoC for a commercially available FPGA board
  ☆68Updated 8 years ago
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆32Updated 2 years ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆46Updated 7 years ago
• zylin / zpugcc
  ☆51Updated 7 years ago
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆53Updated 3 years ago
• mrisc32 / mrisc32
  MRSIC32 ISA documentation and development
  ☆90Updated last year
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆43Updated 2 years ago
• zhemao / ez8
  The Easy 8-bit Processor
  ☆181Updated 10 years ago
• jerry-D / SYMPL-GP-GPU-Compute-Engines
  Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…
  ☆22Updated 6 years ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆116Updated 8 years ago
• knowm / jspice
  JSpice is a SPICE-inspired analog circuit simulator made in Java with an emphasis on simulating memristors and analog circuits containing…
  ☆60Updated 3 years ago
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆51Updated 6 years ago
• riscvarchive / ISA_Formal_Spec_Public_Review
  Locus site for Public Review of Several RISC-V ISA Formal Specs
  ☆73Updated 4 years ago
• secworks / chacha
  Verilog 2001 implementation of the ChaCha stream cipher.
  ☆39Updated last month
• Obijuan / RISC-V-FPGA
  RISC-V CPU for OpenFPGAs, in Icestudio
  ☆89Updated 7 months ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• amal029 / jop
  Instrumented Java Optimized processor
  ☆27Updated 11 years ago
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆55Updated 7 years ago
• riscvarchive / riscv-fesvr
  RISC-V Frontend Server
  ☆62Updated 5 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago