jop-devel / jopLinks
JOP is a Java processor for real-time systems
☆129Updated 11 years ago
Alternatives and similar repositories for jop
Users that are interested in jop are comparing it to the libraries listed below
Sorting:
- Moxie-compatible core repository☆47Updated 5 months ago
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆54Updated 4 years ago
- A reimplementation of a tiny stack CPU☆86Updated 2 years ago
- MRSIC32 ISA documentation and development☆91Updated 2 years ago
- An experimental System-on-Chip with a custom compiler toolchain.☆60Updated 6 years ago
- A user-expandable micro-computer system that runs on an FPGA development board and includes the FORTH software language. The system is cu…☆28Updated 4 months ago
- The BERI and CHERI processor and hardware platform☆50Updated 8 years ago
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆55Updated 6 years ago
- Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools☆126Updated 9 years ago
- a simple C-to-Verilog compiler☆51Updated 8 years ago
- DyRACT Open Source Repository☆16Updated 9 years ago
- Stack CPU Work In Progress☆30Updated 2 years ago
- Tools and Examples for IcoBoard☆80Updated 4 years ago
- ☆54Updated 8 years ago
- Instrumented Java Optimized processor☆33Updated 12 years ago
- An online Verilog IDE based on YosysJS.☆24Updated 10 years ago
- A small JAVA VM for microcontrollers☆33Updated 5 years ago
- Core description files for FuseSoC☆124Updated 5 years ago
- 586 compatible soft core for FPGA in verilog with AXI4 interface☆15Updated 9 years ago
- The Easy 8-bit Processor☆187Updated 11 years ago
- MR1 formally verified RISC-V CPU☆56Updated 7 years ago
- The Zylin ZPU☆248Updated 10 years ago
- One Page CPU Project - CPU, Assembler & Emulator each in a single page of code☆83Updated last year
- Partial implementation of Knuth's MMIX processor (FPGA softcore)☆54Updated 9 months ago
- Simple demo for Lattice iCEstick board as seen on Hackaday☆22Updated 9 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆113Updated 2 years ago
- A (Py)thon (D)SL for (G)enerating (In)struction set simulators.☆166Updated 7 years ago
- A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.☆37Updated 3 years ago
- A RISC-V processor simulator☆29Updated 3 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆45Updated 3 years ago