Alternatives and similar repositories for jop

Users that are interested in jop are comparing it to the libraries listed below

• atgreen / moxie-cores
  Moxie-compatible core repository
  ☆46Updated last year
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆83Updated last year
• zylin / zpugcc
  ☆51Updated 8 years ago
• jamieiles / oldland-cpu
  Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
  ☆125Updated 9 years ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆49Updated 8 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• mrisc32 / mrisc32
  MRSIC32 ISA documentation and development
  ☆90Updated last year
• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆56Updated 5 years ago
• archlabo / Frix
  IBM PC Compatible SoC for a commercially available FPGA board
  ☆71Updated 8 years ago
• cliffordwolf / xbitmanip
  RISC-V XBitmanip Extension
  ☆26Updated 6 years ago
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆53Updated 3 years ago
• parallella / parallella-riscv
  RISC-V port to Parallella Board
  ☆12Updated 8 years ago
• revaldinho / opc
  One Page CPU Project - CPU, Assembler & Emulator each in a single page of code
  ☆82Updated 11 months ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆34Updated 8 years ago
• jerry-D / SYMPL-GP-GPU-Compute-Engines
  Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…
  ☆22Updated 6 years ago
• VladisM / MARK_II
  Simple SoC in VHDL with full toolchain and custom board.
  ☆28Updated 7 years ago
• openrisc / orpsoc-cores
  Core description files for FuseSoC
  ☆124Updated 5 years ago
• chuckb / haikuVM
  A small JAVA VM for microcontrollers
  ☆31Updated 5 years ago
• cornell-brg / pydgin
  A (Py)thon (D)SL for (G)enerating (In)struction set simulators.
  ☆165Updated 7 years ago
• cliffordwolf / icotools
  Tools and Examples for IcoBoard
  ☆80Updated 3 years ago
• zhemao / ez8
  The Easy 8-bit Processor
  ☆183Updated 11 years ago
• m-labs / lm32
  LatticeMico32 soft processor
  ☆106Updated 10 years ago
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆55Updated 8 years ago
• tommythorn / yari
  YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…
  ☆45Updated 6 months ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• zylin / zpu
  The Zylin ZPU
  ☆244Updated 10 years ago
• Ravenslofty / 74xx-liberty
  ☆68Updated 2 years ago
• cseed / cynth
  a simple C-to-Verilog compiler
  ☆51Updated 8 years ago
• combinatorylogic / soc
  An experimental System-on-Chip with a custom compiler toolchain.
  ☆60Updated 5 years ago
• drom / quark
  Stack CPU Work In Progress
  ☆30Updated last year