jasha64 / SNN-FPGA
Spiking Neural Network RTL Implementation
☆41Updated 3 years ago
Related projects: ⓘ
- A repository FPGA-friendly SNN models☆27Updated 3 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆50Updated last year
- FPGA acceleration of a Spike-Timing-Dependent Plasticity learning algorithm for Spiking Neural Networks☆33Updated 4 years ago
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆19Updated 4 years ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆50Updated 3 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆30Updated 4 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆28Updated 5 years ago
- ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.☆152Updated 5 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆16Updated 6 years ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆34Updated last year
- ☆12Updated 3 years ago
- ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.☆71Updated 2 years ago
- ☆81Updated 4 years ago
- ☆12Updated this week
- ☆16Updated 3 years ago
- IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures☆22Updated 5 years ago
- This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator☆14Updated 4 years ago
- FPGA Design of a Spiking Neural Network.☆30Updated 4 months ago
- A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…☆9Updated last year
- A Spiking neural network simulator NEST base on FPGA‘s cluster（LIF NEURON）☆17Updated 4 years ago
- Leaky Integrate and Fire (LIF) model implementation for FPGA☆39Updated 10 months ago
- A nest brain simulator based on FPGA(LIF NEURON)☆13Updated 2 years ago
- A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated …☆34Updated 7 months ago
- Framework for radix encoded SNN on FPGA☆11Updated 2 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆66Updated 2 years ago
- Repository collecting papers about neuromorphic hardware, such as ASIC and FPGA implementations of SNNs and stuff.☆133Updated 10 months ago
- Spiking Neural Network Accelerator☆12Updated 2 years ago
- tpu-systolic-array-weight-stationary☆17Updated 3 years ago
- SATA_Sim is an energy estimation framework for Backpropagation-Through-Time (BPTT) based Spiking Neural Networks (SNNs) training and infe…☆23Updated last month
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆19Updated 3 weeks ago