Small footprint and configurable JESD204B/JESD204C core
☆61Sep 24, 2026Updated last month
Alternatives and similar repositories for litejesd204
Users that are interested in litejesd204 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- JESD204B core for Migen/MiSoC☆37May 5, 2021Updated 5 years ago
- Small footprint and configurable Inter-Chip communication cores☆68Updated this week
- Small footprint and configurable SATA core☆171Oct 19, 2026Updated 2 weeks ago
- Small footprint and configurable embedded FPGA logic analyzer☆213Updated this week
- Small footprint and configurable Ethernet core☆310Updated this week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- FPGA code for reading Hamamatsu C9100 data over cameralink using SPEXI FPGA card.☆23Nov 25, 2015Updated 10 years ago
- Vivado design for basic NeTV2 FPGA with chroma-based overlay☆20Dec 24, 2016Updated 9 years ago
- LiteX based FPGA gateware for Thunderscope.☆31Oct 25, 2026Updated last week
- LiteX based FPGA gateware for Thunderscope.☆28Feb 6, 2024Updated 2 years ago
- Small footprint and configurable SPI core☆48Sep 24, 2026Updated last month
- Finding the bacteria in rotting FPGA designs.☆14Dec 28, 2020Updated 5 years ago
- Test/demo waveform datasets for libscopehal and glscopeclient☆12Oct 5, 2023Updated 3 years ago
- Small footprint and configurable SDCard core☆144Oct 8, 2026Updated 3 weeks ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆14Oct 19, 2026Updated 2 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Tools to convert Kicad intermediate netlist to HDL block diagram netlist☆12Jul 21, 2016Updated 10 years ago
- ☆13Feb 8, 2021Updated 5 years ago
- libsigrok-to-SCPI bridge for use with scopehal. Currently tailored for DSLabs devices.☆20Jul 12, 2023Updated 3 years ago
- ☆18Dec 15, 2025Updated 10 months ago
- USB3 SuperSpeed (5Gbps) and SuperSpeedPlus (10Gbps) for FPGAs without external chip: PHY + Device Core in LiteX.☆274Updated this week
- Small footprint and configurable PCIe core☆740Updated this week
- GNURadio implementation of the lazy Viterbi algorithm☆13May 8, 2020Updated 6 years ago
- MIPI CSI-2 Camera Sensor Receiver V2 Verilog HDL implementation For any generic FPGA. Tested with IMX219 IMX477 on Lattice Crosslink NX w…☆70Feb 13, 2025Updated last year
- ☆13Updated this week
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Digital Modulation Measurements over GNU Radio☆18Nov 3, 2023Updated 3 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆47Jun 22, 2021Updated 5 years ago
- fpga for utrasound mobile device☆13Aug 10, 2015Updated 11 years ago
- Projects for building MIL-STD-1553 communications devices☆35Aug 7, 2024Updated 2 years ago
- Project and presentation for SpaceX Application☆14Jul 21, 2017Updated 9 years ago
- PCIe Screamer - TLPs experiments...☆188Apr 23, 2023Updated 3 years ago
- The hardware implementation of UDP in Bluespec SystemVerilog☆14Jun 3, 2024Updated 2 years ago
- AXI support for Migen/MiSoC☆28Oct 1, 2026Updated last month
- ADRV90xx Getting Started Info☆14Mar 3, 2020Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Designs for the Olimex iCE40HX1K-EVB board☆14Aug 14, 2017Updated 9 years ago
- LiteX development baseboards arround the SQRL Acorn.☆80Oct 19, 2026Updated 2 weeks ago
- Ultimate ECP5 development board☆123Jul 4, 2019Updated 7 years ago
- HiPU200 open-source version is a DNN accelerator, using RISC-V instruction set and customized vector/matrix extension.☆10Jan 7, 2022Updated 4 years ago
- PCIe analyzer experiments☆69May 21, 2020Updated 6 years ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆112Oct 3, 2019Updated 7 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Feb 17, 2026Updated 8 months ago