ring00 / bbl-ucore

Related projects ⓘ

Alternatives and complementary repositories for bbl-ucore

• oscourse-tsinghua / LoongsonCsprj2017-manual
  基于龙芯FPGA开发板的计算机综合系统实验
  ☆25Updated 5 years ago
• TianhuaTao / uCore-SMP
  A Symmetric Multiprocessing OS Kernel over RISC-V
  ☆30Updated 2 years ago
• KuangjuX / hypocaust-2
  hypocaust-2, a type-1 hypervisor with H extension run on RISC-V machine
  ☆50Updated 11 months ago
• kvm-riscv / linux
  Linux KVM RISC-V repo
  ☆49Updated this week
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆34Updated 10 months ago
• jiegec / kb
  My knowledge base
  ☆38Updated last week
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated last year
• riscv-and-rust-and-decaf / riscv32i-cpu-chisel
  riscv32i-cpu
  ☆18Updated 3 years ago
• cnyangkun / nscscc2018
  nscscc2018
  ☆26Updated 6 years ago
• js2xxx / umi
  An RISC-V experimental OS
  ☆25Updated last year
• rustsbi / rustsbi-hifive-unmatched
  RustSBI support on SiFive FU740 board; FU740 is a five-core heterogeneous processor with four SiFive U74 cores, and one SiFive S7 core
  ☆17Updated last year
• oscomp / proj23-lightweight-hypervisor
  在RISC-V处理器上实现一个轻量级的Hypervisor。
  ☆12Updated 3 years ago
• xyongcn / LoongsonCsprj2017
  Computer System Project for Loongson FPGA Board in 2017
  ☆50Updated 6 years ago
• thu-cs-lab / verilog-coding-standard
  Recommended coding standard of Verilog and SystemVerilog.
  ☆33Updated 3 years ago
• shady831213 / terminus
  A riscv isa simulator in rust.
  ☆63Updated last year
• OS-F-4 / usr-intr
  项目的主仓库
  ☆22Updated 2 years ago
• cnyangkun / nscscc2017
  National Student Computer System Capability Challenge
  ☆9Updated 6 years ago
• Oyami-Srk / RISCV-GDB-Paging
  Paging Debug tool for GDB using python
  ☆13Updated 2 years ago
• AlwenXXD / nscscc2021
  龙芯杯21个人赛作品
  ☆35Updated 3 years ago
• xiyurain / UltraOS
  A Rust based Multicore OS developed by UltraTeam, HITsz. Currently updated on https://gitee.com/LoanCold/ultraos_backup
  ☆45Updated 5 months ago
• rcore-os / rcore-user
  User programs for rCore OS
  ☆18Updated 2 years ago
• trivialmips / TrivialMIPS
  MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
  ☆104Updated 5 years ago
• DeathWish5 / rCore_tutorial_tests
  rCore_tutorial_tests
  ☆10Updated 3 years ago
• z4yx / NaiveMIPS-HDL
  Naïve MIPS32 SoC implementation
  ☆113Updated 4 years ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 6 years ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆21Updated last year
• ISRC-CAS / tarsier-oerv
  Project magament for porting openEuler to RISC-V
  ☆33Updated last year
• chenzhiy2001 / code-debug
  支持Rust语言的源代码级操作系统调试工具
  ☆32Updated last week
• siriusdemon / Rare
  Build your own Riscv Emulator in Rust.
  ☆105Updated 2 years ago
• plctlab / plct-toolbox
  PLCT工具箱
  ☆27Updated 2 years ago