Alternatives and similar repositories for bbl-ucore:

Users that are interested in bbl-ucore are comparing it to the libraries listed below

• KuangjuX / hypocaust-2
  hypocaust-2, a type-1 hypervisor with H extension run on RISC-V machine
  ☆55Updated last year
• MaxXSoft / GeeOS
  The Gee (寂) Operating System, written in YuLang.
  ☆34Updated 3 years ago
• TianhuaTao / uCore-SMP
  A Symmetric Multiprocessing OS Kernel over RISC-V
  ☆30Updated 2 years ago
• oscourse-tsinghua / LoongsonCsprj2017-manual
  基于龙芯FPGA开发板的计算机综合系统实验
  ☆25Updated 6 years ago
• MashPlant / lalr1
  An LALR1(1)/LL(1) parser generator in Rust, for multiple languages.
  ☆49Updated 2 years ago
• Lingrui98 / RISC-V-book
  A translation project of the RISC-V reader
  ☆174Updated last year
• typekernel / typekernel
  Warning: 🕳 ahead!
  ☆16Updated 5 years ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• SKTT1Ryze / xv6-k210
  Porting xv6-riscv on k210
  ☆19Updated 3 years ago
• KuangjuX / hypocaust
  hypocaust, a S-mode trap and emulate type-1 hypervisor run on RISC-V machine.
  ☆48Updated 2 years ago
• IPADS-DuVisor / kvm-tutorial
  ☆23Updated last year
• chyyuu / thoughts
  ☆42Updated last year
• shady831213 / terminus
  A riscv isa simulator in rust.
  ☆64Updated last year
• rustsbi / slides
  All public report slides, articles and meeting minutes related to RustSBI
  ☆29Updated this week
• rcore-os / rcore-user
  User programs for rCore OS
  ☆18Updated 2 years ago
• js2xxx / umi
  An RISC-V experimental OS
  ☆25Updated last year
• jiegec / kb
  My knowledge base
  ☆45Updated this week
• z4yx / supervisor-mips32
  计算机组成原理课程32位监控程序
  ☆48Updated 4 years ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆37Updated last year
• HUST-OS / xv6-k210
  Port XV6 to K210 board!
  ☆136Updated 3 years ago
• rustsbi / fast-trap
  快速陷入处理
  ☆34Updated last month
• rustsbi / rustsbi-hifive-unmatched
  RustSBI support on SiFive FU740 board; FU740 is a five-core heterogeneous processor with four SiFive U74 cores, and one SiFive S7 core
  ☆17Updated last year
• Oyami-Srk / RISCV-GDB-Paging
  Paging Debug tool for GDB using python
  ☆13Updated 2 years ago
• xyongcn / LoongsonCsprj2017
  Computer System Project for Loongson FPGA Board in 2017
  ☆52Updated 6 years ago
• plctlab / writing-your-first-riscv-simulator
  《从零开始的RISC-V模拟器开发》配套的PPT和教学资料
  ☆213Updated 3 years ago
• siriusdemon / Rare
  Build your own Riscv Emulator in Rust.
  ☆105Updated 2 years ago
• nbdd0121 / r2vm
  Rust RISC-V Virtual Machine
  ☆96Updated 4 months ago
• OS-F-4 / usr-intr
  项目的主仓库
  ☆23Updated 2 years ago
• rcore-os / aCore
  Asynchronous OS kernel written in Rust.
  ☆34Updated 4 years ago
• cnyangkun / nscscc2017
  National Student Computer System Capability Challenge
  ☆9Updated 6 years ago