Alternatives and similar repositories for bbl-ucore

Users that are interested in bbl-ucore are comparing it to the libraries listed below

• TianhuaTao / uCore-SMP
  A Symmetric Multiprocessing OS Kernel over RISC-V
  ☆32Updated 3 years ago
• KuangjuX / hypocaust-2
  hypocaust-2, a type-1 hypervisor with H extension run on RISC-V machine
  ☆58Updated 2 years ago
• rustsbi / slides
  All public report slides, articles and meeting minutes related to RustSBI
  ☆30Updated 2 weeks ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• OS-F-4 / usr-intr
  项目的主仓库
  ☆25Updated 3 years ago
• skyzh / RISCV-Simulator
  💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visu…
  ☆206Updated 5 years ago
• HUST-OS / xv6-k210
  Port XV6 to K210 board!
  ☆144Updated 4 years ago
• Oyami-Srk / RISCV-GDB-Paging
  Paging Debug tool for GDB using python
  ☆13Updated 3 years ago
• oscomp / proj23-lightweight-hypervisor
  在RISC-V处理器上实现一个轻量级的Hypervisor。
  ☆12Updated 4 years ago
• howardlau1999 / yatcpu
  Yet another toy CPU.
  ☆93Updated 2 years ago
• rustsbi / rustsbi-hifive-unmatched
  RustSBI support on SiFive FU740 board; FU740 is a five-core heterogeneous processor with four SiFive U74 cores, and one SiFive S7 core
  ☆17Updated 2 years ago
• rustsbi / sbi-rt
  Simple RISC-V SBI runtime library; designated for supervisor use
  ☆25Updated last year
• trivialmips / TrivialMIPS
  MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
  ☆108Updated 6 years ago
• js2xxx / umi
  An RISC-V experimental OS
  ☆25Updated 2 years ago
• IPADS-DuVisor / kvm-tutorial
  ☆23Updated 2 years ago
• typekernel / typekernel
  Warning: 🕳 ahead!
  ☆16Updated 5 years ago
• oscourse-tsinghua / LoongsonCsprj2017-manual
  基于龙芯FPGA开发板的计算机综合系统实验
  ☆26Updated 6 years ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 7 years ago
• SKTT1Ryze / xv6-k210
  Porting xv6-riscv on k210
  ☆20Updated 4 years ago
• siriusdemon / Rare
  Build your own Riscv Emulator in Rust.
  ☆106Updated 3 years ago
• chyyuu / thoughts
  ☆42Updated 2 years ago
• Lingrui98 / RISC-V-book
  A translation project of the RISC-V reader
  ☆174Updated last year
• jwnhy / coffer
  Coffer is a RISC-V trusted execution environment developed in Rust.
  ☆21Updated 3 years ago
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 3 years ago
• hakula139 / xv6-armv8
  [WIP] Xv6, a simple Unix-like teaching operating system, re-implemented for ARMv8 (AArch64), written in C
  ☆17Updated 4 years ago
• luojia65 / DailySchedule
  ☆22Updated 4 years ago
• oscomp / proj1-rustsbi
  实现和扩展RISC-V SBI运行时，使之能够支持并运行操作系统
  ☆14Updated 8 months ago
• rcore-os / RVM
  Rcore Virtual Machine
  ☆114Updated last year
• rcore-os / zCore-Tutorial
  [WIP] Tutorial for zCore kernel.
  ☆58Updated 4 years ago
• MashPlant / lalr1
  An LALR1(1)/LL(1) parser generator in Rust, for multiple languages.
  ☆49Updated 3 years ago