Alternatives and similar repositories for rtl_codes

Users that are interested in rtl_codes are comparing it to the libraries listed below

• hbharathbhat / minimally_biased_multipliers
  ☆13Updated last year
• Hrushikraj / maldump
  Malware Samples after unpacking wiull be dumped here.
  ☆11Updated last year
• vipinkmenon / neuralNetwork
  ☆302Updated last year
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆180Updated last year
• Ummidichandrika / 100-Days-of-RTL
  ☆116Updated 2 years ago
• vinayrayapati / rv32i
  Implementation of RISC-V RV32I
  ☆28Updated 3 years ago
• padhi499 / Image-Classification-using-CNN-on-FPGA
  Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.
  ☆163Updated 5 years ago
• visnjicm / verilog-neural-network
  Verilog implementation of a pre-trained handwritten digit recognition simple neural network.
  ☆27Updated 2 years ago
• y-C-x / HDLBits_Solution
  My solution to the problem set on HDLBits.
  ☆26Updated 5 years ago
• Subhasis-Sahu / SFAL-VSD
  ☆13Updated last year
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆59Updated last year
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆74Updated 3 years ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆242Updated 2 years ago
• matbi86 / 01_ai_accelerator_basic_for_student
  ai_accelerator_basic_for_student (no solve)
  ☆14Updated 5 years ago
• AniketBadhan / Convolutional-Neural-Network
  Implementation of CNN using Verilog
  ☆241Updated 8 years ago
• fayizferosh / soc-design-and-planning-nasscom-vsd
  2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…
  ☆31Updated last year
• suchuankai / CNN-hw-accelerator
  CNN hardware accelerator to accelerate quantized LeNet-5 model
  ☆43Updated 2 years ago
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆103Updated last year
• EkthaReddy / RISC-V-Single-Cycle-Processor
  In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…
  ☆20Updated last year
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆330Updated last year
• JeffreySamuel / canny_edge_detection_in_FPGA
  In this project, Canny edge detection, one of the efficient edge detection algorithms is implemented on a Zedboard FPGA using verilog. Th…
  ☆23Updated 4 years ago
• Vidhi24-hub / 100daysofrtl
  ☆16Updated last year
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆165Updated last year
• Devipriya1921 / Traffic-Light-Controller-using-Verilog
  Verilog Project
  ☆21Updated 4 years ago
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆108Updated 2 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆180Updated 6 years ago
• kerryliukk / NTHU-ICLAB
  清華大學 | 積體電路設計實驗 (IC LAB) | 110上
  ☆47Updated 3 years ago
• Mattjesc / Efficient-FPGA-CNN-Accelerator
  Efficient FPGA-Based Accelerator for Convolutional Neural Networks
  ☆41Updated last year
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆407Updated last year
• chrisneuf / Deep-Neural-Network-Hardware-Accelerator
  My implementation of an FPGA Deep Neural Network Hardware Accelerator, moved from my bitbucket
  ☆27Updated 6 years ago