Alternatives and similar repositories for VHDLFormatter

Users that are interested in VHDLFormatter are comparing it to the libraries listed below

• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated this week
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 10 months ago
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆59Updated 3 weeks ago
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆58Updated last month
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆228Updated last month
• FPHDL / fphdl
  VHDL-2008 Support Library
  ☆57Updated 9 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆82Updated 3 years ago
• kevinpt / symbolator
  HDL symbol generator
  ☆198Updated 2 years ago
• suoto / fpga_cores
  ☆33Updated 2 years ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆72Updated last year
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆64Updated 4 years ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆50Updated 3 years ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆70Updated 2 months ago
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆191Updated 2 years ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆77Updated last week
• vhdl-linter / vhdl-linter
  ☆30Updated last year
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆38Updated 9 months ago
• alexforencich / cocotbext-i2c
  I2C models for cocotb
  ☆38Updated 3 months ago
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆26Updated last year
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆128Updated 6 months ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆58Updated 3 weeks ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 4 months ago
• VLSI-EDA / PoC-Examples
  This repository contains synthesizable examples which use the PoC-Library.
  ☆39Updated 4 years ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆80Updated 3 weeks ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆42Updated 2 months ago
• VHDL / Interfaces
  Interface definitions for VHDL-2019.
  ☆34Updated last week
• wallento / wavedrompy
  WaveDrom compatible python command line
  ☆111Updated 2 years ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆69Updated last week
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆142Updated last year