Kelvinyu1117 / LSQ-implementationLinks
This is an unofficial implementation of the paper - LEARNED STEP SIZE QUANTIZATION at ICLR 2020
☆8Updated 4 years ago
Alternatives and similar repositories for LSQ-implementation
Users that are interested in LSQ-implementation are comparing it to the libraries listed below
Sorting:
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 3 years ago
- BSQ: Exploring Bit-Level Sparsity for Mixed-Precision Neural Network Quantization (ICLR 2021)☆40Updated 4 years ago
- AFP is a hardware-friendly quantization framework for DNNs, which is contributed by Fangxin Liu and Wenbo Zhao.☆13Updated 3 years ago
- Open-source of MSD framework☆16Updated last year
- Unofficial implementation of LSQ-Net, a neural network quantization framework☆298Updated last year
- bitfusion verilog implementation☆10Updated 3 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆12Updated 3 years ago
- ☆27Updated 3 months ago
- PyTorch implementation for the APoT quantization (ICLR 2020)☆277Updated 7 months ago
- Reproducing Quantization paper PACT☆64Updated 3 years ago
- Quantized Training for Convolutional Neural Networks using Xilinx Brevitas☆11Updated 3 years ago
- ☆19Updated 3 years ago
- ☆44Updated 2 years ago
- An FPGA Accelerator for Transformer Inference☆85Updated 3 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆49Updated last year
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 2 years ago
- CMix-NN: Mixed Low-Precision CNN Library for Memory-Constrained Edge Devices☆44Updated 5 years ago
- The PyTorch implementation of Learned Step size Quantization (LSQ) in ICLR2020 (unofficial)☆135Updated 4 years ago
- Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts☆122Updated last year
- ☆18Updated 2 years ago
- ☆12Updated 3 months ago
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53Updated 7 years ago
- ☆11Updated 5 years ago
- LSQ+ or LSQplus☆69Updated 5 months ago
- Implementation network trimming using pytorch☆14Updated 5 years ago
- The goal of this design is to use the PYNQ-Z2 development board to design a general convolution neural network accelerator. And through r…☆11Updated 4 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆113Updated 4 years ago
- Fast Emulation of Approximate DNN Accelerators in PyTorch☆23Updated last year
- ☆29Updated this week