In this VLSI design course, we explored topics such as HLS programming, combination circuits, sequential circuits, and a capstone project. From high-level synthesis to hands-on application, this course covers essential aspects of digital circuit design.
☆13Jul 23, 2024Updated 2 years ago
Alternatives and similar repositories for NIELIT-INTERNSHIP-ON-HLS-PROGRAMMING
Users that are interested in NIELIT-INTERNSHIP-ON-HLS-PROGRAMMING are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 5 stage pipeline implementation of RISC-V 32I Processor.☆10Nov 27, 2024Updated last year
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆21Aug 19, 2024Updated 2 years ago
- Advanced Physical Design Using OpenLANE/SKY130 course notes by Ojasvi Shah☆17Oct 19, 2024Updated 2 years ago
- ☆26Nov 11, 2025Updated 11 months ago
- This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop hel…☆23Jul 5, 2021Updated 5 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- A demo of running a custom object detection model on Raspberry Pi☆16Sep 14, 2022Updated 4 years ago
- ☆13Feb 17, 2025Updated last year
- Source Code☆31Apr 4, 2024Updated 2 years ago
- Computer Vision project built-in Python to use hand gestures to play virtual games.☆12Jan 12, 2021Updated 5 years ago
- Coherent Cobination Propagation and Modeling☆10Jul 23, 2020Updated 6 years ago
- A RTL-based project in Verilog that shows real-time video captured by a CMOS camera OV7670 and displayed on a monitor through VGA at 640 …☆33Mar 18, 2023Updated 3 years ago
- ☆22Jan 21, 2017Updated 9 years ago
- FIR band-pass filter using Verilog HDL.☆14Sep 7, 2026Updated 2 months ago
- Tutorials and Things to Do while Hunting Vulnerability.☆11Apr 25, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This repo is tutorial on how to contribute to Vyommedha SoC☆12Sep 18, 2025Updated last year
- AMBA bus lecture material☆11Jan 21, 2020Updated 6 years ago
- Trying to fine tune the configurations of the convolutional layers of a deep learning architecture☆10Nov 11, 2020Updated 5 years ago
- This repository contains lectures designed for an introduction to RISC-v and it's capabilities.☆18Aug 22, 2026Updated 2 months ago
- A vision transformer based framework for classifying executable images as benign or malicious☆11Mar 19, 2024Updated 2 years ago
- TCL Script automating the frontend of ASIC design☆11Jun 21, 2023Updated 3 years ago
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Jul 19, 2022Updated 4 years ago
- This document aims to agree on a broad, international strategy for the implementation of open scholarship that meets the needs of differe…☆11Dec 10, 2018Updated 7 years ago
- A web-based handwritten digit recognizer with neural network visualization. See the activations of every neuron in real-time as your digi…☆11Jan 18, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆14Nov 7, 2021Updated 5 years ago
- 🚀 Real-Time High-Level Synthesis (HLS) Projects for UltraScale+ FPGAs. Accelerated design pipelines, dataflow architectures, and low-lat…☆16Aug 2, 2026Updated 3 months ago
- ☆15Sep 27, 2022Updated 4 years ago
- Learning Path: RISC-V & Advanced Edge AI on SiFive FE310-G002 SoC | 32-bit RISC-V | 320 MHz | 16KB L1 Instruction Cache | 128Mbit (16MB) …☆12Sep 18, 2025Updated last year
- Convolutional Neural Network in C (for educational purposes)☆32Jan 18, 2021Updated 5 years ago
- Submission template for Tiny Tapeout 04☆17Jun 15, 2024Updated 2 years ago
- This is our Compiler Design project for 6th semester.☆12May 15, 2022Updated 4 years ago
- ☆14Sep 29, 2024Updated 2 years ago
- SystemVerilog RTL Linter for YoSys☆24Nov 22, 2024Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- 5 days (30 hours) is all what took me to learn the basics and design a pipelined RV32I core. Check this article to know more !☆14Feb 2, 2022Updated 4 years ago
- FIR Filter in Verilog☆15Nov 17, 2019Updated 6 years ago
- Libraries that implement and clients that utilize the Mink-IPC interface☆15Updated this week
- Laser propagation model☆10Jul 1, 2025Updated last year
- This repository contains the details and the code for the MIPS32 ISA based RISC Processor, which is implemented in 5 stage pipelined conf…☆23Apr 26, 2023Updated 3 years ago
- FPGA with Xilinx Vitis HLS, Vivado, Vitis, and ZYNQ board. Working with HLS, Matrix Multiplier with HLS☆16Mar 1, 2021Updated 5 years ago
- Swept Source Optical Coherence Tomography☆11Jun 20, 2016Updated 10 years ago
Are these results useful?