A tiny Verilog CNN accelerator for the Tang Nano 20K. Features INT8 quantized weights, a streaming MAC array, and full on-chip MNIST inference.
☆17May 26, 2026Updated 5 months ago
Alternatives and similar repositories for cnn_chip
Users that are interested in cnn_chip are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- a collection of CUDA Kernels☆18Jul 24, 2026Updated 3 months ago
- A kernel visualization that walks through each step of the code.☆14Aug 1, 2026Updated 2 months ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆15Dec 23, 2022Updated 3 years ago
- 10 Gigabit Ethernet MAC Core UVM Verification☆19Oct 5, 2023Updated 3 years ago
- A from-scratch GPU stack: custom SIMT hardware in Verilog → a 16-bit ISA + assembler → J++, a small C-like language and compiler — all ru…☆28Sep 29, 2026Updated last month
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Tensor computing core☆15Jul 8, 2026Updated 3 months ago
- A complete UVM TB for verification of single port 64KB RAM☆18Apr 16, 2021Updated 5 years ago
- 從入門到進階的 Chisel HDL 指南☆14Jun 4, 2026Updated 4 months ago
- Image Stiching for Panoramic Images☆10May 15, 2013Updated 13 years ago
- ☆16Mar 27, 2024Updated 2 years ago
- Collection of resources for the Alibaba Cloud AS02MC04 Kintex KU3P UltraScale+ board☆24Jan 6, 2026Updated 9 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆46Jan 6, 2023Updated 3 years ago
- Implementation of the core Transformer architecture in pure C☆14Sep 8, 2024Updated 2 years ago
- Practices related to the fundamental level of the programming language Verilog.☆13Jan 16, 2023Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆16Jan 14, 2021Updated 5 years ago
- A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.☆16Aug 7, 2022Updated 4 years ago
- ☆21Jan 13, 2026Updated 9 months ago
- 2-core MIPS R10K OoO Processor with Snooping MSI and Pipeline Bus☆14Jan 5, 2018Updated 8 years ago
- To take down the code that I've written in course.☆11Jun 23, 2024Updated 2 years ago
- An 8 input interrupt controller written in Verilog.☆31Mar 22, 2012Updated 14 years ago
- Learning Path: RISC-V & Advanced Edge AI on SiFive FE310-G002 SoC | 32-bit RISC-V | 320 MHz | 16KB L1 Instruction Cache | 128Mbit (16MB) …☆12Sep 18, 2025Updated last year
- This repository includes codes created for a graduate level Perception course at the University of Maryland. The repo includes codes for …☆17Oct 24, 2017Updated 9 years ago
- Literature-fetching & citation-auditing skill for LLM agents (Claude/Codex) — 讓 AI 引用經得起追問:找文獻、查核引用真偽與支持度、文獻支撐寫作,防幻覺引用。☆32Oct 14, 2026Updated 2 weeks ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆22Dec 10, 2018Updated 7 years ago
- ☆32Updated this week
- Course material for Purdue ECE57000 Artificial Intelligence☆16Nov 8, 2018Updated 7 years ago
- The course contest involves a multi-player capture-the-flag variant of Pacman, where agents control both Pacman and ghosts in coordinated…☆12Jan 24, 2021Updated 5 years ago
- 👻 Simple Undertale-like game on Basys3 FPGA written in Verilog☆16Jul 3, 2020Updated 6 years ago
- PC Fingerprinter☆11Aug 9, 2018Updated 8 years ago
- Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be eff…☆17Aug 26, 2021Updated 5 years ago
- Slides of Dr Sparsh Mittal on "Computer Architecture for AI" (aka Hardware Architecture for Deep Learning) Course☆20Apr 20, 2026Updated 6 months ago
- ☆26Oct 6, 2025Updated last year
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Bot…☆17Aug 21, 2018Updated 8 years ago
- this repository contains all the ip projects presented in the HLS/RISC-V/Computer Architecture book written by Goossens and published by …☆30Sep 5, 2025Updated last year
- As a proof of concept I wrote this in bash to assist in cathcing Apache OOM or death by swapping problems. Apachetuner.sh is superceded b…☆13Oct 13, 2011Updated 15 years ago
- Learning a bit of assembly programming☆13Mar 23, 2015Updated 11 years ago
- An inhouse RISC-V 32-bits CPU☆22Oct 21, 2026Updated last week
- Showing entropy analysis examples for different data types. example.sh was used to generate. It utilizes cyphunks libdisorder branch and …☆13Dec 24, 2014Updated 11 years ago
- Synchronous FIFOs designed in Verilog/System Verilog.☆26Dec 21, 2025Updated 10 months ago