Xilinx / meta-openamp
☆20Updated 3 months ago
Alternatives and similar repositories for meta-openamp:
Users that are interested in meta-openamp are comparing it to the libraries listed below
- ☆21Updated last week
- Yocto Project layer enables AMD Xilinx tools related metadata for MicroBlaze, Zynq, ZynqMP and Versal devices.☆59Updated last month
- an abstraction layer across user-space Linux, baremetal, and RTOS environments☆24Updated last week
- meta-petalinux distro layer supporting Xilinx Tools☆89Updated 3 months ago
- Repo Manifests for the Yocto Project Build System☆32Updated 3 months ago
- ☆17Updated last year
- Simple AMP Running Linux and Bare-Metal System on Both Zynq SoC Processors☆20Updated 9 years ago
- Repository used to support automated builds under PetaLinux tools that use Yocto.☆59Updated last month
- Collection of Yocto Project layers to enable AMD Xilinx products☆154Updated last week
- This is a wiki and code sharing for ZYNQ☆71Updated 9 years ago
- PolarFire SoC yocto Board Support Package☆54Updated last month
- bootgen source code☆43Updated last week
- This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…☆67Updated 7 years ago
- PolarFire SoC Documentation☆55Updated 2 weeks ago
- Yocto/OE meta layer to add OpenAMP support to your BSP or distro☆51Updated 8 months ago
- This buildroot fork contains customized recipes for generating AMD-Xilinx SoC and Intel SoC embedded Linux images for use with MathWorks …☆25Updated 6 months ago
- ☆111Updated last month
- ☆14Updated 2 years ago
- Example design for the Ethernet FMC using the hard GEMs of the Zynq☆55Updated last week
- Linux Repository for digilent boards☆87Updated 4 months ago
- ☆55Updated 2 years ago
- Xilinx Soft-IP HDMI Rx/Tx core Linux drivers☆41Updated last week
- Source code for reference designs applications☆22Updated 2 months ago
- This repository contains Embedded Linux kernel source code for Xilinx devices.☆22Updated 7 months ago
- ☆14Updated last month
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆33Updated 7 years ago
- Old Altera BSP layer for OpenEmbedded/Yocto Project ( please use https://github.com/altera-opensource/meta-intel-fpga-refdes)☆47Updated last year
- Documentation relevant to the available repositories on RISCV-on-Microsemi-FPGA☆13Updated 6 years ago
- ☆69Updated 9 months ago
- Simple C snippet to transfer DMA memory with scatter/gather on a Zynq 7020☆54Updated 8 years ago