Alternatives and similar repositories for arm2riscv

Users that are interested in arm2riscv are comparing it to the libraries listed below

• riscv / riscv-j-extension
  Working Draft of the RISC-V J Extension Specification
  ☆191Updated last week
• intel / intel-sdsi
  ☆48Updated last month
• riscv-admin / graphics
  Graphics SIG organizational information
  ☆40Updated last year
• sifiveinc / wake
  The SiFive wake build tool
  ☆91Updated last week
• fwsGonzo / bigassm
  Assemble 128-bit RISC-V
  ☆46Updated last year
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆50Updated last year
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆78Updated this week
• openpower-cores / a2o
  ☆142Updated 3 years ago
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• jhhuh / tinyemu
  Fabrice Bellard's tinyemu (https://bellard.org/tinyemu/)
  ☆66Updated 4 years ago
• riscv-non-isa / riscv-semihosting
  ☆32Updated last week
• OpenPOWERFoundation / a2o
  The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …
  ☆51Updated 7 months ago
• pc2 / sus-compiler
  A new Hardware Design Language that keeps you in the driver's seat
  ☆122Updated this week
• openhwgroup / corev-llvm-project
  ☆18Updated last year
• pydrofoil / pydrofoil
  A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one
  ☆83Updated last week
• preames / public-notes
  A collection of (public) notes on assorted topics
  ☆79Updated 4 months ago
• riscv-non-isa / riscv-brs
  The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSV…
  ☆57Updated this week
• riscv-non-isa / riscv-device-tree-doc
  RISC-V Specific Device Tree Documentation
  ☆42Updated last year
• ArchC / ArchC
  A powerful and modern open-source architecture description language.
  ☆46Updated 8 years ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆99Updated 3 years ago
• westerndigitalcorporation / RISC-V-Linux
  This repository provides a Linux kernel bootable on RISC-V boards from SiFive
  ☆170Updated 5 years ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆162Updated 3 years ago
• noteed / riscv-hello-asm
  Bare metal RISC-V assembly hello world
  ☆63Updated 4 years ago
• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆154Updated last month
• shacron / sled
  Sled System Emulator
  ☆28Updated 2 months ago
• hrw / arm-socs-table
  Table of ARM SoC and their features
  ☆61Updated 3 weeks ago
• tenstorrent / tt-umd
  User-Mode Driver for Tenstorrent hardware
  ☆36Updated this week
• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆223Updated last year
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆151Updated last week