roboticslab-uc3m / fpga-nnLinks
NN on FPGA
☆22Updated 8 years ago
Alternatives and similar repositories for fpga-nn
Users that are interested in fpga-nn are comparing it to the libraries listed below
Sorting:
- Python Jupyter Notebooks and FPGA designs showcasing what myHDL can do over traditional Verilog or VHDL☆36Updated 6 years ago
- Monitor and display signal waveforms from your MyHDL/nMigen digital design in a Jupyter notebook.☆40Updated last year
- Yosys Plugins☆21Updated 6 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated last year
- Repository and Wiki for Chip Hack events.☆51Updated 3 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- Dual MikroBUS board for Upduino 2 FPGA☆18Updated 7 years ago
- SPI core☆14Updated 5 years ago
- RISC-V CPU for OpenFPGAs, in Icestudio☆92Updated last year
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Updated 6 years ago
- Virtual Development Board☆60Updated 3 years ago
- FPGA development in PlatformIO, using the Icestorm opensource toolchain☆21Updated 8 years ago
- Lattice iCE40 FPGA experiments - Work in progress☆105Updated 4 years ago
- This is a simple UART echo test for the iCEstick Evaluation Kit☆38Updated 6 years ago
- Export netlists from Yosys to DigitalJS☆51Updated last year
- FPGA 101 - Workshop materials☆76Updated 6 years ago
- Torc: Tools for Open Reconfigurable Computing☆39Updated 8 years ago
- OpenFPGA☆34Updated 7 years ago
- Open Processor Architecture☆26Updated 9 years ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆36Updated 4 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆90Updated 6 years ago
- 100% open source dev kit for EOS S3 MCU+eFPGA SoC supported by fully open source SDK and FPGA Toolchain☆62Updated 3 years ago
- This repository contains software for BeagleWire. It is a realization of my project for GSOC-2017☆46Updated 6 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆30Updated 7 months ago
- Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)☆21Updated 9 years ago
- iCE40 floorplan viewer☆24Updated 7 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆65Updated this week
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆46Updated last year
- A mixed signal netlist language (pre-alpha)☆61Updated 6 years ago
- understanding the tinyfpga bootloader☆24Updated 7 years ago