NN on FPGA
☆22Jun 10, 2017Updated 9 years ago
Alternatives and similar repositories for fpga-nn
Users that are interested in fpga-nn are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- IP cores for the FPGA Libre project☆12Aug 7, 2017Updated 9 years ago
- AlexForth for 6809 processor☆10Jun 2, 2024Updated 2 years ago
- FPGA Portable Music Generator☆11Aug 1, 2018Updated 8 years ago
- multi protocol interface tool☆23Aug 29, 2017Updated 8 years ago
- Simple Jupiter Ace implementation for the Ice40 (myStorm BlackIce)☆12Jan 28, 2018Updated 8 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Dual MikroBUS board for Upduino 2 FPGA☆18May 24, 2018Updated 8 years ago
- ☆17Sep 20, 2025Updated 10 months ago
- All CPU and MCU documentation in one place☆16Oct 25, 2016Updated 9 years ago
- simple wishbone client to read buttons and write leds☆19Nov 30, 2023Updated 2 years ago
- The code for an FPGA softcore comparison☆11Jun 21, 2020Updated 6 years ago
- Space Invaders in Verilog for the iCE40 H1K☆17Feb 15, 2024Updated 2 years ago
- Huffman encoder☆10Sep 8, 2013Updated 12 years ago
- Minimal ZX Spectrum for Ulx3s ECP5 board☆12May 7, 2020Updated 6 years ago
- RADIX-4 SRT division☆13Oct 31, 2019Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.☆10Jul 12, 2023Updated 3 years ago
- This repository contains all the materials for the Hackaday Supercon 2019 Pasadena FPGA Badge workshops☆49Dec 7, 2019Updated 6 years ago
- ☆25Jan 16, 2019Updated 7 years ago
- An open source FPGA Enigma Machine created with Icestudio and Verilog☆20Nov 1, 2019Updated 6 years ago
- An attempt to reverse engineer a bitstream made for an AL3-10 FPGA☆16Jan 6, 2023Updated 3 years ago
- JPEG Compression RTL implementation☆11Aug 19, 2017Updated 8 years ago
- Repositorio del libro Inteligencia artificial para el Z80☆21Mar 21, 2026Updated 4 months ago
- J-core SOC for ice40 FPGA☆20Dec 8, 2019Updated 6 years ago
- Projects using the Sipeed Tang Primer FPGA development board☆17Dec 6, 2020Updated 5 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- unsigned Radix-2 SRT division,基2除法☆17May 12, 2015Updated 11 years ago
- UVM Python Verification Agents Library☆15Mar 18, 2021Updated 5 years ago
- STM32F042-based USB to SPI device for programming iCE40 FPGAs☆18Nov 30, 2022Updated 3 years ago
- Adding UVM support to Icarus Verilog (and Verilator in near future) by taking a step-by-step, bottom-up approach.☆24Dec 27, 2022Updated 3 years ago
- Tiny VGA Pmod board designed in KiCad☆25Sep 4, 2024Updated last year
- CamelForth Z80☆15Nov 25, 2020Updated 5 years ago
- ☆13Aug 22, 2022Updated 3 years ago
- Peak : Processor Specification Language ala Newell and Bell's ISP☆21Dec 5, 2023Updated 2 years ago
- PCIe stack written in Amaranth.☆17Apr 27, 2026Updated 3 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 7 years ago
- digilogic is a high speed digital circuit simulator / schematic capture☆36Jul 15, 2026Updated 3 weeks ago
- Manage your ESP32 SD Card FAT32 files with a simple web based interface☆14Jan 12, 2022Updated 4 years ago
- Automatically generates a written step-by-step tutorial with graphics for a part created in FreeCAD Part Design☆13Dec 15, 2023Updated 2 years ago
- A Goldschmidt integer divider written in verilog. Similar to Newton-Raphson but the divison step can be pipelined.☆16Apr 25, 2024Updated 2 years ago
- Weekly update for SG2042 ecosystem. RISC-V is inevitable!☆22Jul 11, 2025Updated last year
- Multicomp Z80 CP/M implementation for the Ice40 (myStorm BlackIce)☆17Apr 23, 2018Updated 8 years ago