sophgocommunity / SG2042-Newsletter
Weekly update for SG2042 ecosystem. RISC-V is inevitable!
☆22Updated last week
Alternatives and similar repositories for SG2042-Newsletter:
Users that are interested in SG2042-Newsletter are comparing it to the libraries listed below
- ☆86Updated last week
- A extremely size-optimized RV32I soft processor for FPGA.☆27Updated 6 years ago
- ☆42Updated 3 years ago
- ☆28Updated last month
- GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……☆98Updated 3 months ago
- AIA IP compliant with the RISC-V AIA spec☆36Updated 2 months ago
- ☆85Updated 2 years ago
- ☆33Updated 8 months ago
- The ISA specification for the ZiCondOps extension.☆19Updated last year
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆35Updated last year
- RTL blocks compatible with the Rocket Chip Generator☆14Updated 9 months ago
- Biweekly Sync Meeting for RISC-V Software Ecosystem. Meeting time is more friendly for people living in East Asia.☆23Updated last week
- ☆31Updated last week
- ☆29Updated 2 years ago
- RISC-V Configuration Structure☆37Updated 4 months ago
- A bare-metal application to test specific features of the risc-v hypervisor extension☆37Updated last year
- GDB server to debug CPU simulation waveform traces☆44Updated 3 years ago
- Documentation of the RISC-V C API☆76Updated last month
- Setup scripts and files needed to compile CoreMark on RISC-V☆65Updated 8 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆30Updated 10 months ago
- RISC-V Nexus Trace TG documentation and reference code☆50Updated 2 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆94Updated 3 years ago
- The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.☆27Updated 3 years ago
- This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…☆46Updated this week
- Dual-issue RV64IM processor for fun & learning☆58Updated last year
- Chisel Cheatsheet☆33Updated last year
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆143Updated 4 months ago
- Linux KVM RISC-V repo☆56Updated last week
- A gdbstub for connecting GDB to a RISC-V Debug Module☆27Updated 5 months ago
- GDB Server for interacting with RISC-V models, boards and FPGAs☆21Updated 5 years ago