viniul / delayAVFLinks
☆10Updated 6 months ago
Alternatives and similar repositories for delayAVF
Users that are interested in delayAVF are comparing it to the libraries listed below
Sorting:
- ☆25Updated 2 years ago
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆67Updated 2 months ago
- This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.☆23Updated last year
- Proof-of-concept for I See Dead Micro-Ops transient execution attack☆14Updated 3 years ago
- The artifact for SecSMT paper -- Usenix Security 2022☆27Updated 2 years ago
- ☆16Updated last year
- CleanupSpec (MICRO-2019)☆17Updated 4 years ago
- ☆86Updated last year
- ☆35Updated 4 years ago
- Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly☆15Updated 4 years ago
- Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)☆129Updated 9 months ago
- ☆18Updated 2 years ago
- The open-source component of Prime+Scope, published at CCS 2021☆31Updated last year
- The code in this project demonstrates 2 novel Spectre-V4 attacks, named as out-of-place Spectre-STL and Spectre-CTL, based on the Specula…☆21Updated last year
- A Ghidra static analysis tool for locating PACMAN Gadgets☆13Updated 2 years ago
- Defeating Pointer Authentication on the Apple M1 with Hardware Attacks☆43Updated 2 years ago
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆64Updated 5 years ago
- Streamline Covert Channel Attack (presented in ASPLOS'21)☆20Updated 4 years ago
- M1 bare metal project in Rust☆31Updated 2 years ago
- Proof of concept code for the BranchSpec exploit.☆9Updated 2 years ago
- ☆19Updated 2 years ago
- HW interface for memory caches☆28Updated 5 years ago
- Repository containing the guide and code for booting RISC-V full system linux using gem5.☆52Updated 4 years ago
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆60Updated 5 years ago
- A tool for checking the contract satisfaction for hardware designs☆11Updated 6 months ago
- Medusa Repository: Transynther tool and Medusa Attack☆21Updated 4 years ago
- Hardware-assisted Dynamic Information Flow Tracking for Runtime Protection on RISC-V☆10Updated last year
- Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser☆61Updated 2 years ago
- Using Data Memory-Dependent Prefetchers to Leak Data at Rest☆36Updated 2 years ago
- Open-source release of "Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud" (ASPLOS '24)☆22Updated 2 months ago