Alternatives and similar repositories for SpicePy

Users that are interested in SpicePy are comparing it to the libraries listed below

• RTimothyEdwards / XCircuit
  XCircuit circuit drawing and schematic capture tool
  ☆119Updated 3 months ago
• wrcad / xictools
  XicTools: Xic graphical editor, WRspice circuit simulator, and accessories. for electronic design.
  ☆170Updated last week
• ngspice / ngspice
  ☆170Updated last year
• skuep / GDS3D
  Fork from https://sourceforge.net/projects/gds3d
  ☆68Updated last year
• PySpice-org / PySpice
  Simulate electronic circuit using Python and the Ngspice / Xyce simulators
  ☆736Updated 11 months ago
• gmagno / spyci
  A tiny Python package to parse spice raw data files.
  ☆54Updated 2 years ago
• imr / ngspice
  mirror of ngspice repo at git://git.code.sf.net/p/ngspice/ngspice ngspice-ngspice
  ☆215Updated this week
• Qucs / ADMS
  ADMS is a code generator for some of Verilog-A
  ☆100Updated 2 years ago
• trilomix / GDS3D
  GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input …
  ☆227Updated 10 months ago
• Xyce / Xyce
  The Xyce™ Parallel Electronic Simulator
  ☆69Updated last month
• capn-freako / PyBERT
  Serial communication link bit error rate tester simulator, written in Python.
  ☆110Updated this week
• donghoonpark / ltspice_pytool
  Spice data analysis tool for python
  ☆118Updated 2 years ago
• idea-fasoc / OpenFASOC
  Fully Open Source FASOC generators built on top of open-source EDA tools
  ☆283Updated 2 weeks ago
• efabless / OpenLane
  This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …
  ☆152Updated last year
• TinyTapeout / siliwiz
  Silicon Layout Wizard
  ☆173Updated last month
• Isotel / mixedsim
  Hardware Design Tool - Mixed Signal Simulation with Verilog
  ☆79Updated 6 months ago
• StefanSchippers / xschem
  A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…
  ☆393Updated last week
• eelab-dev / EEcircuit
  A browser-based SPICE circuit simulator
  ☆129Updated this week
• drifter1 / circuitsim
  Implementing a full-on electronic circuit simulator, studying the whole concept and physics behind it!
  ☆56Updated 4 years ago
• ahkab / ahkab
  a SPICE-like electronic circuit simulator written in Python
  ☆367Updated last year
• dwarning / VA-Models
  Verilog-A simulation models
  ☆74Updated last week
• mph- / lcapy
  Lcapy is a Python package for symbolic linear circuit analysis and signal processing. It uses SymPy for symbolic mathematics.
  ☆267Updated 3 months ago
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆276Updated last year
• RTimothyEdwards / qflow
  Qflow full end-to-end digital synthesis flow for ASIC designs
  ☆216Updated 8 months ago
• knowm / jspice
  JSpice is a SPICE-inspired analog circuit simulator made in Java with an emphasis on simulating memristors and analog circuits containing…
  ☆61Updated 3 years ago
• purdue-onchip / gds2Para
  GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
  ☆119Updated 2 years ago
• Nubis-Communications / SignalIntegrity
  Python tools for signal integrity applications
  ☆151Updated 2 weeks ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆338Updated 4 months ago
• chipsalliance / silicon-notebooks
  ☆169Updated last year
• cdelker / schemdraw
  ☆159Updated 3 weeks ago