Alternatives and similar repositories for beamerthemeLUH

Users that are interested in beamerthemeLUH are comparing it to the libraries listed below

• sifferman / schematics
  Examples of how to Generate Schematics from SystemVerilog Synthesis Tools
  ☆22Updated last year
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆111Updated this week
• davidthings / hdelk
  Web-based HDL diagramming tool
  ☆79Updated 2 years ago
• Kuree / hgdb
  Hardware generator debugger
  ☆74Updated last year
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆155Updated last month
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆39Updated last week
• google / skywater-pdk-sky130-raw-data
  Raw data collected about the SKY130 process technology.
  ☆57Updated 2 years ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆46Updated 9 months ago
• efabless / mpw_precheck
  ☆42Updated 4 months ago
• librelane / librelane
  ASIC implementation flow infrastructure
  ☆47Updated last week
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆59Updated 8 months ago
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆46Updated 8 months ago
• esa-tu-darmstadt / BSVTools
  ☆17Updated 6 months ago
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆95Updated last week
• merledu / caravan
  A caravan equipped with API for creating bus protocols in Chisel with ease.
  ☆14Updated 3 months ago
• google / bigspicy
  ☆41Updated 2 years ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆64Updated 8 months ago
• semify-eda / fstdumper
  Verilog VPI module to dump FST (Fast Signal Trace) databases
  ☆16Updated last year
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆48Updated 3 weeks ago
• wallento / riscv-python-model
  Python Model of the RISC-V ISA
  ☆51Updated 2 years ago
• ShonTaware / RISC-V_Core_4_Stage
  RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set
  ☆15Updated 4 years ago
• chipsalliance / silicon-notebooks
  ☆169Updated last year
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆112Updated last year
• wavedrom / cli
  CLI for WaveDrom
  ☆62Updated last year
• pulp-platform / fpu_ss
  CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor
  ☆11Updated 8 months ago
• bluespec / AWSteria_Infra
  "Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)
  ☆19Updated 9 months ago
• bmurmann / COCOA
  COCOA: Collaborative Compendium on Analog Integrated Circuits
  ☆19Updated 3 months ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆45Updated last year
• jonpry / Pill
  Skill language interpreter
  ☆66Updated 4 years ago