本Project結合了碩士班上課的內容、書籍「CPU自制入門」、書籍「自己動手寫CPU」來完成一個MIPS32架構的CPU。
☆22Feb 23, 2022Updated 4 years ago
Alternatives and similar repositories for OpenMIPS_KIMWENG_sopc
Users that are interested in OpenMIPS_KIMWENG_sopc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)☆162Sep 9, 2024Updated last year
- ☆18Mar 23, 2023Updated 3 years ago
- For my MSc final dissertation "Beamforming Optimization for Reconfigurable Intelligent Surfaces-Assisted Integrated Sensing and Communic…☆17Sep 1, 2024Updated last year
- Implementation of FA-VAE: Frequancy Augmented VAE☆13May 5, 2023Updated 2 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆29Jan 21, 2025Updated last year
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- This repo is "NTHU VLSI System Design and Implementation" course project.☆13Mar 5, 2017Updated 9 years ago
- 透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍 ，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。☆18Oct 25, 2023Updated 2 years ago
- ☆26Apr 9, 2020Updated 6 years ago
- Play Atari(Breakout) Game by DRL - DQN, Noisy DQN and A3C☆15May 30, 2020Updated 5 years ago
- ☆22Aug 1, 2020Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆45Sep 26, 2023Updated 2 years ago
- 💻 A 5-stage pipeline MIPS CPU implementation in Verilog.☆34Jul 5, 2020Updated 5 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆49Dec 3, 2023Updated 2 years ago
- Linux 讀書會☆44Sep 17, 2021Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Discussion Forum for High-Level Synthesis (HLS) Courses in Taiwan.☆57Sep 5, 2023Updated 2 years ago
- 3×3脉动阵列乘法器☆51Sep 18, 2019Updated 6 years ago
- 實作《自己動手寫CPU》書上的程式碼☆69Sep 16, 2018Updated 7 years ago
- NCTU 2021 Spring Integrated Circuit Design Laboratory☆203Apr 2, 2023Updated 3 years ago
- ☆47Feb 27, 2024Updated 2 years ago
- LaTeX Template of Thesis for National Yang Ming Chiao Tung University (NYCU)☆60Feb 23, 2025Updated last year
- Verilog implementation of various types of CPUs☆78Sep 27, 2019Updated 6 years ago
- 中正大學，資工系，羅習五，系統程式設計課程☆74Apr 21, 2025Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆186Apr 4, 2026Updated 3 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 書籍「C 語言教學手冊 第四版」練習題我的解答，約於 2016 年左右完成，供同為自學的夥伴參考。☆91Apr 16, 2023Updated 3 years ago
- A window system for resource-constrained devices☆116Updated this week
- 超詳細 ICLAB 2024 Spring 修課心得 & 修課指南，含資源整理☆127Apr 9, 2025Updated last year
- This is a detailed SystemVerilog course☆153Mar 4, 2025Updated last year
- 🚀 AwesomeCS is the document lets you know how to build your own OS on RISC-V platform.☆101Feb 25, 2022Updated 4 years ago
- 我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆114Dec 15, 2021Updated 4 years ago
- 簡單的 socket programming 入門筆記。☆140Feb 4, 2023Updated 3 years ago
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆10Aug 6, 2025Updated 8 months ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆186Jun 20, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆197Jul 23, 2018Updated 7 years ago
- A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding☆164May 20, 2022Updated 3 years ago
- 程式導師實驗計畫第三期☆184Apr 13, 2020Updated 6 years ago
- ☆372Sep 12, 2025Updated 7 months ago
- ☆392Apr 13, 2023Updated 3 years ago
- The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…☆501Jul 18, 2025Updated 9 months ago
- Rocket Chip Generator☆3,750Apr 21, 2026Updated last week