本Project結合了碩士班上課的內容、書籍「CPU自制入門」、書籍「自己動手寫CPU」來完成一個MIPS32架構的CPU。
☆22Feb 23, 2022Updated 4 years ago
Alternatives and similar repositories for OpenMIPS_KIMWENG_sopc
Users that are interested in OpenMIPS_KIMWENG_sopc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)☆165Sep 9, 2024Updated last year
- Include NachOS MP1 ~ MP4 and Pthread (2022-09 ~ 2023-01).☆54Jan 26, 2023Updated 3 years ago
- Post-quantum cryptography (PQC) - Falcon☆17Apr 15, 2025Updated last year
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆30Jan 21, 2025Updated last year
- 透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。☆19Oct 25, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆26Apr 9, 2020Updated 6 years ago
- Play Atari(Breakout) Game by DRL - DQN, Noisy DQN and A3C☆15May 30, 2020Updated 6 years ago
- Implement DQN and DDQN algorithm on Atari games，such as BreakoutNoFrameskip-v4, PongNoFrameskip-v4,BoxingNoFrameskip-v4.☆15Jun 30, 2020Updated 5 years ago
- ☆22Aug 1, 2020Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆45Sep 26, 2023Updated 2 years ago
- ☆34Jun 8, 2023Updated 3 years ago
- 💻 A 5-stage pipeline MIPS CPU implementation in Verilog.☆34Jul 5, 2020Updated 5 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆49Dec 3, 2023Updated 2 years ago
- Linux 讀書會☆44Sep 17, 2021Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Discussion Forum for High-Level Synthesis (HLS) Courses in Taiwan.☆58Sep 5, 2023Updated 2 years ago
- 3×3脉动阵列乘法器☆50Sep 18, 2019Updated 6 years ago
- NCTU 2021 Spring Integrated Circuit Design Laboratory☆205Apr 2, 2023Updated 3 years ago
- ☆48Feb 27, 2024Updated 2 years ago
- LaTeX Template of Thesis for National Yang Ming Chiao Tung University (NYCU)☆64Feb 23, 2025Updated last year
- Enable Google Location History in regions not available.☆77Sep 29, 2021Updated 4 years ago
- Verilog implementation of various types of CPUs☆81Sep 27, 2019Updated 6 years ago
- 中正大學，資工系，羅習五，系統程式設計課程☆74May 25, 2026Updated 2 weeks ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆187Apr 4, 2026Updated 2 months ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆123Jan 26, 2013Updated 13 years ago
- 書籍「C 語言教學手冊 第四版」練習題我的解答，約於 2016 年左右完成，供同為自學的夥伴參考。☆90Apr 16, 2023Updated 3 years ago
- Official Python wrapper for OpenFHE.☆153May 19, 2026Updated 2 weeks ago
- 超詳細 ICLAB 2024 Spring 修課心得 & 修課指南，含資源整理☆137Apr 30, 2026Updated last month
- 🚀 AwesomeCS is the document lets you know how to build your own OS on RISC-V platform.☆102Feb 25, 2022Updated 4 years ago
- y86 simulator and assembler written in Javascript.☆34May 10, 2025Updated last year
- 簡單的 socket programming 入門筆記。☆142Feb 4, 2023Updated 3 years ago
- A python implementation of the signature scheme Falcon☆197Jan 13, 2026Updated 4 months ago
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆13Aug 6, 2025Updated 10 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆187Jun 20, 2024Updated last year
- A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding☆164May 20, 2022Updated 4 years ago
- Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。☆163Jan 20, 2019Updated 7 years ago
- 程式導師實驗計畫第三期☆185Apr 13, 2020Updated 6 years ago
- ☆382Sep 12, 2025Updated 8 months ago
- The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…☆522Jul 18, 2025Updated 10 months ago
- Rocket Chip Generator☆3,783Updated this week