azonenberg / antikernel

Related projects: ⓘ

• whitequark / Boneless-CPU
  Resource-efficient 16-bit CPU architecture for FPGA control plane
  ☆92Updated 9 months ago
• nitram2342 / degate
  Open source software for chip reverse engineering.
  ☆168Updated 3 years ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆45Updated 7 years ago
• cseed / cynth
  a simple C-to-Verilog compiler
  ☆47Updated 7 years ago
• cliffordwolf / icotools
  Tools and Examples for IcoBoard
  ☆79Updated 3 years ago
• combinatorylogic / soc
  An experimental System-on-Chip with a custom compiler toolchain.
  ☆59Updated 4 years ago
• azonenberg / openfpga
  Open FPGA tools
  ☆257Updated 4 years ago
• atgreen / moxie-cores
  Moxie-compatible core repository
  ☆45Updated 8 months ago
• cliffordwolf / xbitmanip
  RISC-V XBitmanip Extension
  ☆27Updated 5 years ago
• brouhaha / glacial
  Glacial - microcoded RISC-V core designed for low FPGA resource utilization
  ☆82Updated 4 years ago
• libresilicon / process
  ☆87Updated 5 years ago
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆53Updated 3 years ago
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆41Updated 5 years ago
• knielsen / ice40_viewer
  ☆57Updated 11 months ago
• RobertBaruch / riscv-reboot
  ☆42Updated 3 years ago
• riscvarchive / ISA_Formal_Spec_Public_Review
  Locus site for Public Review of Several RISC-V ISA Formal Specs
  ☆73Updated 4 years ago
• mrisc32 / mrisc32
  MRSIC32 ISA documentation and development
  ☆89Updated last year
• jamesbowman / j1
  The J1 CPU
  ☆161Updated 3 years ago
• betrusted-io / betrusted-soc
  Betrusted main SoC design
  ☆135Updated 9 months ago
• betrusted-io / betrusted-ec
  Betrusted embedded controller (UP5K)
  ☆44Updated 8 months ago
• leviathanch / qtflow
  A Qt5 based free VLSI development tool
  ☆30Updated 6 years ago
• gatecat / prjoxide
  Documenting Lattice's 28nm FPGA parts
  ☆143Updated 8 months ago
• Wolfgang-Spraul / fpgatools
  public domain tools for FPGAs
  ☆324Updated 7 years ago
• howerj / bit-serial
  A bit-serial CPU written in VHDL, with a simulator written in C.
  ☆116Updated 2 weeks ago
• cornell-brg / pydgin
  A (Py)thon (D)SL for (G)enerating (In)struction set simulators.
  ☆165Updated 6 years ago
• swetland / gateware
  A collection of little open source FPGA hobby projects
  ☆45Updated 4 years ago
• whitequark / Yumewatari
  妖刀夢渡
  ☆55Updated 5 years ago
• jamieiles / oldland-cpu
  Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
  ☆119Updated 8 years ago
• m-labs / misoc
  The original high performance and small footprint system-on-chip based on Migen™
  ☆305Updated 4 months ago
• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆54Updated 4 years ago