ra3xdh / qucs
This repository is archived. Use Qucs-S instead
☆25Updated 3 years ago
Alternatives and similar repositories for qucs:
Users that are interested in qucs are comparing it to the libraries listed below
- Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)☆21Updated 9 years ago
- This project is dedicated to building an ElectroMagnetic workbench for FreeCAD. FreeCAD is a free 3D parametric CAD. FreeCAD is used as p…☆62Updated last year
- Hardware Design Tool - Mixed Signal Simulation with Verilog☆77Updated 4 months ago
- A C++ library to describe geometrical objects and their physical or non-physical properties.☆37Updated 3 weeks ago
- Signal analyzer CSV to IEEE 1364-2001 VCD file format converter.☆11Updated 3 years ago
- ☆30Updated 4 years ago
- FastHenry is the premium inductance solver originally developed at M.I.T. on Unix platform. A de-facto golden reference standard, FastHen…☆60Updated 5 years ago
- This repository contain source code for ngspice and ghdl integration☆30Updated 4 months ago
- Yosys Plugins☆21Updated 5 years ago
- This package provides a gnucap based qucsator implementation.☆13Updated this week
- Circuit simulator of the Qucs project☆28Updated 4 months ago
- ADMS is a code generator for some of Verilog-A☆100Updated 2 years ago
- Custom IC Creator (ciccreator) is a compiler that takes in a object definition file (JSON), a SPICE file, and a design rule file and outp…☆27Updated last month
- A simple function to add wavedrom diagrams into an ipython notebook.☆22Updated 3 years ago
- Altium PCB project for the Titan PCI Express development card. This card uses the Lattice ECP5 FPGA.☆19Updated 10 years ago
- gnucap mirror (read only)☆25Updated last week
- openEMS High-level layer☆18Updated 2 months ago
- ☆59Updated last year
- HDMI Expansion Modules compatible with the Pmod standard☆11Updated 7 years ago
- The 64 bit OpenPOWER Microwatt core, MPW1 tape out☆17Updated 3 years ago
- Small footprint and configurable JESD204B core☆42Updated 2 weeks ago
- A mixed signal netlist language (pre-alpha)☆60Updated 6 years ago
- Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verific…☆12Updated 6 years ago
- iCE40 floorplan viewer☆24Updated 6 years ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- An automatic schematic generation tool which generates schematics from a SPICE netlist, usually of output from qflow.☆23Updated 4 years ago
- A KiCad wizard to assist you in making footprints for chips having pins around the edges (SOICs, QFPs, etc.) and ball grid arrays (BGAs)☆37Updated 5 years ago
- Monitor and display signal waveforms from your MyHDL/nMigen digital design in a Jupyter notebook.☆40Updated last year
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- A VHDL frontend for Yosys☆102Updated 8 years ago