Alternatives and similar repositories for turbo_decoder

Users that are interested in turbo_decoder are comparing it to the libraries listed below

• OpenResearchInstitute / dvb_fpga
  RTL implementation of components for DVB-S2
  ☆131Updated 2 years ago
• catkira / complex_multiplier
  HDL code for a complex multiplier with AXI stream Interface
  ☆14Updated 2 years ago
• phthinh / OFDM_802_11
  IEEE 802.11 OFDM-based transceiver system
  ☆43Updated 8 years ago
• ekigwana / adi_dmac_iio_client
  Client Driver for this HDL module: https://github.com/analogdevicesinc/hdl/tree/master/library/axi_dmac
  ☆17Updated 3 years ago
• analogdevicesinc / TransceiverToolbox
  MATLAB toolbox for ADI transceiver products
  ☆64Updated 3 weeks ago
• strath-sdr / rfsoc_ofdm
  PYNQ example of an OFDM Transmitter and Receiver on RFSoC.
  ☆59Updated last week
• Grootzz / AD9361_TX_MSK
  A project demonstrate how to config ad9361 to TX mode and how to transmit MSK
  ☆62Updated 6 years ago
• catkira / open5G_phy
  A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog
  ☆222Updated 9 months ago
• Teddy-van-Jerry / sdr-psk-fpga
  Dual-Mode PSK Transceiver on SDR With FPGA
  ☆51Updated last year
• yugithub / OFDM-baseband
  Verilog实现OFDM基带
  ☆45Updated 10 years ago
• MicroPhase / antsdr-fw
  ANTSDR Firmware
  ☆141Updated 2 years ago
• xdsopl / LDPC
  Playing with Low-density parity-check codes
  ☆99Updated 2 years ago
• dshekhalev / FEC
  FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)
  ☆129Updated last month
• MeowLucian / SDR_Matlab_LTE
  Using Software Designed Radio to transmit LTE downlink signals at 2.4 GHz
  ☆45Updated 6 years ago
• freecores / dvb_s2_ldpc_decoder
  DVB-S2 LDPC Decoder
  ☆29Updated 11 years ago
• srsran / zynq_timestamping
  Open source Zynq timestamping implementation from Software Radio Systems (SRS)
  ☆76Updated 3 years ago
• Grootzz / AD9361_TX_GMSK
  A project demonstrate how to config ad9361 to TX mode and how to transmit GMSK
  ☆16Updated 7 years ago
• analogdevicesinc / ad936x-filter-wizard
  MATLAB-based FIR filter design
  ☆62Updated last year
• MicroPhase / antsdr_standalone
  Standalone application based on ADI hdl and no_OS for ANTSDR.
  ☆23Updated 10 months ago
• jfoshea / Viterbi-Decoder-in-Verilog
  An efficient implementation of the Viterbi decoding algorithm in Verilog
  ☆60Updated last year
• analogdevicesinc / u-boot-xlnx
  Deprecated ADI fork ➡️ analogdevicesinc/u-boot
  ☆18Updated 2 months ago
• strath-sdr / rfsoc_qpsk
  PYNQ example of using the RFSoC as a QPSK transceiver.
  ☆112Updated last week
• mehrdadh / lora-modulator
  LoRa modulator implementation on Lattice ECP5 FPGA to interface with AT86RF215 I/Q Radio
  ☆41Updated 11 months ago
• Lcrypto / FEC-Archive-Verilog
  Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…
  ☆80Updated 2 years ago
• OpenResearchInstitute / DVB-receiver
  Work being done on the DVB-receiver for Phase 4 Ground.
  ☆59Updated 2 years ago
• strath-sdr / rfsoc_qsfp_offload
  RFSoC QSFP Data Offload Design with GNU Radio
  ☆26Updated last year
• jgaeddert / liquid-wlan
  Open-source 802.11a WLAN PHY
  ☆66Updated 4 years ago
• Xilinx / RFSoC2x2-PYNQ
  RFSoC2x2 board repo for PYNQ
  ☆17Updated 3 years ago
• strath-sdr / rfsoc_frequency_planner
  An RFSoC Frequency Planner developed using Python.
  ☆32Updated 2 years ago
• phthinh / OFDM_802_16
  IEEE 802.16 OFDM-based transceiver system
  ☆28Updated 6 years ago