ISRC-CAS / tarsier-oerv
Project magament for porting openEuler to RISC-V
☆34Updated last year
Alternatives and similar repositories for tarsier-oerv:
Users that are interested in tarsier-oerv are comparing it to the libraries listed below
- A Symmetric Multiprocessing OS Kernel over RISC-V☆30Updated 2 years ago
- RISC-V VM in Bash☆24Updated 2 weeks ago
- PoC LoongArch - RISC-V emulator☆32Updated last year
- RustSBI support on SiFive FU740 board; FU740 is a five-core heterogeneous processor with four SiFive U74 cores, and one SiFive S7 core☆17Updated last year
- My knowledge base☆50Updated this week
- Unofficial LoongArch Intrinsics Guide☆51Updated 3 weeks ago
- 调试大师:你见过最强的内核调试器☆35Updated 3 years ago
- Towards a million-node RISC-V cluster.☆13Updated last month
- ☆42Updated last year
- Tsinghua Advanced Networking Labs on FPGA☆38Updated 5 months ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- 可运行OS的RISCV-64的硬件模拟器设计与实现☆22Updated 4 years ago
- Backend & Frontend for JieLabs☆22Updated 2 years ago
- ☆16Updated 3 weeks ago
- Kendryte K210 SBI support using RustSBI, provides privileged spec 1.12 environment by emulating it using 1.9.1☆36Updated last year
- An RISC-V experimental OS☆25Updated last year
- Collection of Loongson products' public documentation☆74Updated 3 weeks ago
- 各类内核的设计思路☆19Updated 3 years ago
- Examine and discover LoongArch instructions☆15Updated last year
- ☆23Updated last year
- Yet another toy CPU.☆91Updated last year
- RuyiSDK Package Manager☆21Updated this week
- ☆23Updated 3 years ago
- Open-source RISC-V cryptographic hardware token, RTL repo☆19Updated 2 years ago
- LoongArch Opcodes (unofficially compiled list)☆38Updated 3 months ago
- Some notes or translations about operating system or programming language.☆96Updated 5 months ago
- Compile Optimization Guided Binary Translator (using llvm as infrastructure)☆47Updated 8 months ago
- Source-level operating system debugging tool that supports debugging kernel and multiple user processes synchronously. VSCode integration…☆37Updated last week
- Build your own Riscv Emulator in Rust.☆105Updated 2 years ago
- User-mode trap-and-emulate hypervisor for RISC-V☆13Updated 3 years ago