Huawei-CPLLab / SYCLops
A SYCL-specific LLVM-to-MLIR converter
☆1Updated last year
Related projects ⓘ
Alternatives and complementary repositories for SYCLops
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆53Updated last month
- IREE plugin repository for the AMD AIE accelerator☆69Updated this week
- ☆80Updated this week
- Vector math library using RISC-V vector ISA via C intrinsic☆11Updated 2 weeks ago
- A scalable High-Level Synthesis framework on MLIR☆228Updated 6 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆56Updated this week
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆64Updated this week
- ☆37Updated 8 months ago
- The University of Bristol HPC Simulation Engine☆93Updated last week
- Bridging polyhedral analysis tools to the MLIR framework☆102Updated last year
- Benchmarks for Accelerator Design and Customized Architectures☆116Updated 4 years ago
- ☆84Updated 9 months ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆44Updated last year
- HeteroCL-MLIR dialect for accelerator design☆40Updated 2 months ago
- ☆57Updated last year
- An out-of-tree MLIR dialect template.☆91Updated 2 months ago
- A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…☆19Updated last year
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆88Updated last week
- Release of stream-specialization software/hardware stack.☆116Updated last year
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆135Updated last year
- Allo: A Programming Model for Composable Accelerator Design☆146Updated this week
- ☆37Updated 4 months ago
- EQueue Dialect☆39Updated 2 years ago
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆81Updated last month
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- RiVEC Bencmark Suite☆105Updated 2 weeks ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆80Updated last month
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆113Updated last week
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆63Updated 5 years ago
- A hardware synthesis framework with multi-level paradigm☆37Updated last year