Alternatives and similar repositories for NahiViva

Users that are interested in NahiViva are comparing it to the libraries listed below

• ryuz / jelly
  Original FPGA platform
  ☆68Updated last week
• polyphony-dev / polyphony
  Polyphony is Python based High-Level Synthesis compiler.
  ☆105Updated 5 months ago
• i4kimura / chip_architect
  Translation of http://chip-architect.com/news/2003_09_21_Detailed_Architecture_of_AMDs_64bit_Core.html
  ☆11Updated 6 years ago
• ryuz / BinaryBrain
  Binary Neural Network Framework for FPGA(Differentiable LUT)
  ☆162Updated last month
• kadomoto / poyo-v
  Open source RISC-V IP core for FPGA/ASIC design
  ☆31Updated last year
• kazunori279 / CPU32
  Tiny MIPS for Terasic DE0
  ☆36Updated 11 years ago
• fixstars / xg_mac
  10G Ethernet MAC implementation
  ☆21Updated 5 years ago
• panda5mt / KyogenRV
  The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
  ☆46Updated 4 years ago
• ikanoano / arty-videocap
  Repeat and capture the video signal with Digilent Arty-A7 and a video extender board.
  ☆15Updated 4 years ago
• nlsynth / karuta
  Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…
  ☆106Updated 3 years ago
• shibatchii / RISC-V
  RISC-V documentation transrate to Japanese.
  ☆73Updated 3 years ago
• msyksphinz-self / swimmer_riscv
  Instruction set simulator for RISC-V
  ☆53Updated 4 years ago
• ciniml / seccamp_riscv_cpu
  セキュリティ・キャンプ 2022-2024 RISC-V CPU自作ゼミ 資料置き場
  ☆37Updated 3 months ago
• takasehideki / asp3_gr_peach_vscode
  TOPPERS/ASP3のVisual Studio Code向けビルド環境
  ☆10Updated 5 years ago
• icf3 / zevios
  original 8bit CPU of ICF3-Z
  ☆12Updated 5 years ago
• 771-8bit / SerialMonitorEssential
  ☆29Updated 6 months ago
• ciniml / seccamp_2022_riscv_cpu
  セキュリティキャンプ 2022 Y4 RISC-V CPU自作ゼミ 講義資料
  ☆29Updated 11 months ago
• istellartech / OpenMOMO
  Sounding Rocket "MOMO"
  ☆65Updated 4 years ago
• iwatake2222 / DeviceDriverLesson
  組み込みLinuxデバイスドライバの実装方法
  ☆66Updated 7 years ago
• cpuex2019-yokyo / core
  RISC-V (rv32imf) CPU implemented in System Verilog for cpuex2019 @ UTokyo
  ☆13Updated 5 years ago
• horie-t / homemade-riscv
  『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ
  ☆13Updated 5 years ago
• vengineer-systemverilog / All-of-SystemVerilog
  みんなのSystemVerilog
  ☆19Updated 3 years ago
• shioyadan / advanced-computer-organization
  ☆161Updated 10 months ago
• tmatsuya / wiki
  ☆38Updated 8 years ago
• ikwzm / ZynqMP-FPGA-Linux
  FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq Ultrascale+ MPSoC)
  ☆130Updated last year
• aquaxis / synverll
  ☆14Updated 9 years ago
• HirokiNakahara / GUINNESS
  GUINNESS: A GUI-based binarized deep Neural NEtwork SyntheSizer toward an FPGA
  ☆181Updated 5 years ago
• i4kimura / chisel-minicpu
  ☆14Updated 5 years ago
• synthesijer / synthesijer
  ☆52Updated 11 months ago
• HirokiNakahara / FPGA_lecture
  Source Codes for a lecture entitled "Parallel and Reconfigurable VLSI Computing" in Tokyo Tech.
  ☆28Updated 4 years ago