Alternatives and similar repositories for NahiViva:

Users that are interested in NahiViva are comparing it to the libraries listed below

• ryuz / jelly
  Original FPGA platform
  ☆59Updated this week
• kadomoto / poyo-v
  Open source RISC-V IP core for FPGA/ASIC design
  ☆30Updated 8 months ago
• polyphony-dev / polyphony
  Polyphony is Python based High-Level Synthesis compiler.
  ☆103Updated last month
• ryuz / BinaryBrain
  Binary Neural Network Framework for FPGA(Differentiable LUT)
  ☆154Updated 3 months ago
• shibatchii / RISC-V
  RISC-V documentation transrate to Japanese.
  ☆73Updated 3 years ago
• panda5mt / KyogenRV
  The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
  ☆44Updated 3 years ago
• nlsynth / karuta
  Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…
  ☆102Updated 3 years ago
• wakwak-koba / AkizukiHistory
  秋月電子の購入履歴詳細を全件ダウンロードします
  ☆21Updated last year
• KyotoMicrocomputer / solid-rapi4
  SOLID for Raspberry Pi 4
  ☆33Updated 9 months ago
• kazunori279 / CPU32
  Tiny MIPS for Terasic DE0
  ☆35Updated 11 years ago
• i4kimura / chip_architect
  Translation of http://chip-architect.com/news/2003_09_21_Detailed_Architecture_of_AMDs_64bit_Core.html
  ☆11Updated 6 years ago
• iwatake2222 / DeviceDriverLesson
  組み込みLinuxデバイスドライバの実装方法
  ☆62Updated 7 years ago
• 771-8bit / SerialMonitorEssential
  ☆28Updated 2 months ago
• bit-trade-one / RasPi-Zero-One-Series
  Raspberry Pi Zero用拡張基板 “ゼロワン”シリーズ
  ☆17Updated 2 months ago
• ciniml / seccamp_2022_riscv_cpu
  セキュリティキャンプ 2022 Y4 RISC-V CPU自作ゼミ 講義資料
  ☆28Updated 6 months ago
• tomozh / PortPop
  シリアルポートが着脱されたときにポート名をバルーン表示で知らせるアプリ
  ☆71Updated 4 years ago
• puhitaku / tepra-lite-esp32
  MicroPython module to communicate with KING JIM TEPRA Lite LR30
  ☆50Updated 3 years ago
• ciniml / seccamp_riscv_cpu
  セキュリティ・キャンプ 2022-2024 RISC-V CPU自作ゼミ 資料置き場
  ☆37Updated 3 months ago
• shioyadan / advanced-computer-organization
  ☆155Updated 6 months ago
• cpuex2019-yokyo / core
  RISC-V (rv32imf) CPU implemented in System Verilog for cpuex2019 @ UTokyo
  ☆13Updated 5 years ago
• YujiToshinaga / RPi64Toppers
  TOPPERS Software for Raspberry Pi AArch64.
  ☆15Updated 6 years ago
• vengineer-systemverilog / All-of-SystemVerilog
  みんなのSystemVerilog
  ☆19Updated 2 years ago
• horie-t / homemade-riscv
  『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ
  ☆13Updated 5 years ago
• tomabou / cpu_core
  ☆9Updated 5 years ago
• istellartech / OpenMOMO
  Sounding Rocket "MOMO"
  ☆65Updated 4 years ago
• ikwzm / ZynqMP-FPGA-Linux
  FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq Ultrascale+ MPSoC)
  ☆130Updated last year
• miyo / learning_fpga
  ☆9Updated 4 years ago
• ikanoano / arty-videocap
  Repeat and capture the video signal with Digilent Arty-A7 and a video extender board.
  ☆15Updated 3 years ago
• algyan / XIAOGYAN
  ☆55Updated last year
• betaEncoder / USB-PD_Adapter
  USB-PD 電源取り出し基板
  ☆21Updated 3 years ago