Agent Skill for creating UESTC course report templates for Claude Code and Codex
☆29May 8, 2026Updated 2 months ago
Alternatives and similar repositories for uestcreport-skill
Users that are interested in uestcreport-skill are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 简单的未优化的SRT除法器☆12Jun 16, 2024Updated 2 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆15Dec 23, 2022Updated 3 years ago
- Attentionlego☆13Jan 24, 2024Updated 2 years ago
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆20Updated this week
- ☆15Mar 22, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- 复微杯☆17Aug 7, 2024Updated last year
- SystemVerilog Implementations of CUDA/TensorCore/TPU GEMM Operations☆22Apr 12, 2026Updated 3 months ago
- Write a CPU from scratch! (5-stage pipeline & 2-way-cache)☆20Jul 18, 2019Updated 7 years ago
- Design a Low-cost-AI-Accelerator based on Google's Tensor Processing Unit Version 1.☆23Jul 11, 2026Updated 2 weeks ago
- ☆21Feb 10, 2025Updated last year
- Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.☆35Aug 9, 2024Updated last year
- 大三上做的本科毕设，包含BNN的替代梯度训练，verilog电路实现，完成180nm工艺流片。☆26Jun 30, 2025Updated last year
- 该项目主要展示了一般的claude code配置方法，并结合官方插件，将claude code嵌入vscode中，此外，实现了claude code与matlab之间的通信，并集成在vscode中，从而达到自动matlab代码编辑，脚本生成，结果保存，代码自动debug等功…☆26May 22, 2026Updated 2 months ago
- Hardware Design and Verification of a configurable and parametrized 50th order low-pass FIR filter starting from MATLAB Modeling to Veril…☆32Mar 4, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆26Aug 10, 2025Updated 11 months ago
- An educational Operating system written by Jack Wang.☆28Mar 18, 2023Updated 3 years ago
- Bilinear interpolation realizes image scaling based on FPGA☆33Jul 11, 2020Updated 6 years ago
- 包含了SOC设计中的通用IP，如外设、总线结构、基础、验证等☆148Apr 30, 2026Updated 2 months ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆39Aug 13, 2024Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆59May 10, 2021Updated 5 years ago
- ☆40Jul 28, 2025Updated last year
- ☆55Jan 14, 2021Updated 5 years ago
- ☆62Feb 18, 2019Updated 7 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- AI Agent开发全链路手册：开发，测试，基座☆94May 22, 2026Updated 2 months ago
- ☆98Jun 6, 2024Updated 2 years ago
- 中国理工科专业研究生毕业论文写作skill / graduate-thesis-polish skill☆115Apr 22, 2026Updated 3 months ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆66Jun 1, 2022Updated 4 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆110Updated this week
- A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL☆98Dec 5, 2019Updated 6 years ago
- An AI accelerator implementation with Xilinx FPGA☆91Jan 29, 2025Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆132Dec 17, 2023Updated 2 years ago
- 我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆122Dec 15, 2021Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- [ICRA-2024] MMAUD: A comprehensive multi-modal anti-UAV dataset for modern miniature drone threats☆243Feb 27, 2026Updated 5 months ago
- PLIC Specification☆154Jul 20, 2026Updated last week
- A FPGA Based CNN accelerator, following Google's TPU V1.☆176Jul 25, 2019Updated 7 years ago
- riscv指令集，单周期以及五级流水线CPU☆133Jan 6, 2025Updated last year
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆191Jun 20, 2024Updated 2 years ago
- 青龙脚本，完成 i茅台 预约申购、登录、短信验证码、耐力值和小茅运领取、旅行 等功能☆446Nov 20, 2025Updated 8 months ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆238Jul 3, 2026Updated 3 weeks ago