Agent Skill for creating UESTC course report templates for Claude Code and Codex
☆29May 8, 2026Updated 4 months ago
Alternatives and similar repositories for uestcreport-skill
Users that are interested in uestcreport-skill are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 简单的未优化的SRT除法器☆12Jun 16, 2024Updated 2 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆15Dec 23, 2022Updated 3 years ago
- all kind of notes, I maybe sort this in the future☆13Aug 29, 2025Updated last year
- ☆15Mar 22, 2024Updated 2 years ago
- Standardizing scientific research drawing skills can make the scientific research drawing process more standardized and reduce AI illusio…☆57May 20, 2026Updated 3 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 复微杯☆18Aug 7, 2024Updated 2 years ago
- SystemVerilog Implementations of CUDA/TensorCore/TPU GEMM Operations☆21Apr 12, 2026Updated 4 months ago
- Deploy llama2.c on the OpenLA500 SoC with custom AI accelerator (FPGA)☆23Jun 16, 2026Updated 2 months ago
- A reusable skill for reproducible Origin/OriginPro figure generation driven by external Python scripts.☆65Aug 2, 2026Updated last month
- Design a Low-cost-AI-Accelerator based on Google's Tensor Processing Unit Version 1.☆23Updated this week
- ☆20Feb 10, 2025Updated last year
- Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.☆34Aug 9, 2024Updated 2 years ago
- ☆30Jun 19, 2025Updated last year
- 大三上做的本科毕设,包含BNN的替代梯度训练,verilog电路实现,完成180nm工艺流片。☆27Jun 30, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Open IP in Hardware Description Language.☆32Sep 4, 2023Updated 3 years ago
- Bilinear interpolation realizes image scaling based on FPGA☆33Jul 11, 2020Updated 6 years ago
- 包含了SOC设计中的通用IP,如外设、总线结构、基础、验证等☆150Apr 30, 2026Updated 4 months ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆39Aug 13, 2024Updated 2 years ago
- ☆91May 27, 2026Updated 3 months ago
- 128KB AXI cache (32-bit in, 256-bit out)☆59May 10, 2021Updated 5 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆39Nov 30, 2022Updated 3 years ago
- ☆43Jul 28, 2025Updated last year
- 🎓 深度教学模式 AI Skill — 让 AI 在每一步编程操作后自动输出专家级技术解析卡片,从「代做」变为「教做」☆147May 19, 2026Updated 3 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Clarvi simple RISC-V processor for teaching☆58Aug 25, 2017Updated 9 years ago
- ☆56Jan 14, 2021Updated 5 years ago
- ☆62Feb 18, 2019Updated 7 years ago
- 中文核心期刊_skill☆202Aug 2, 2026Updated last month
- A small SoC with a pipeline 32-bit RISC-V CPU.☆66Jun 1, 2022Updated 4 years ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆74Aug 10, 2024Updated 2 years ago
- 龙芯杯个人赛工具包(适用于个人赛的golden_trace工具)☆66Mar 6, 2024Updated 2 years ago
- A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL☆98Dec 5, 2019Updated 6 years ago
- AXI总线连接器☆109Mar 26, 2020Updated 6 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- 嘉立创EDA专业版AI SKILL,为AI编程工具提供完整的EasyEDA Pro API接口和WebSocket桥接能力。EasyEDA Pro AI SKILL provides a complete EasyEDA Pro API interface and WebS…☆643Aug 27, 2026Updated last week
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆134Dec 17, 2023Updated 2 years ago
- 一些青龙自用自动打卡功能:wps、OPPO、贝锐☆230Feb 21, 2025Updated last year
- PLIC Specification☆156Jul 20, 2026Updated last month
- verilog实现TPU中的脉动阵列计算卷积的module☆175May 10, 2025Updated last year
- A FPGA Based CNN accelerator, following Google's TPU V1.☆176Jul 25, 2019Updated 7 years ago
- 符合nature论文学术表达和科研绘图的Skill☆39,878Updated this week