sahandKashani / SoC-FPGA-Design-Guide
Tutorial for using the DE1-SoC/DE0-Nano-SoC boards for bare-metal and linux programming
☆66Updated 6 years ago
Alternatives and similar repositories for SoC-FPGA-Design-Guide:
Users that are interested in SoC-FPGA-Design-Guide are comparing it to the libraries listed below
- Examples using the Cyclone V SoC chip☆107Updated 5 years ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 6 years ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆96Updated 2 years ago
- Hardware, Linux Driver and Library for the Zynq AXI DMA interface☆100Updated 6 years ago
- ☆69Updated 3 weeks ago
- Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL☆161Updated last year
- Example design for the Ethernet FMC using the hard GEMs of the Zynq☆54Updated 4 months ago
- Vivado build system☆68Updated 3 months ago
- This is a wiki and code sharing for ZYNQ☆71Updated 9 years ago
- Source code from the MicroZed Chronicles blog hosted by Xcell Daily Blog☆190Updated 6 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆64Updated 4 months ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆101Updated 6 years ago
- Demonstration of the AXI DMA engine on the MicroZed☆26Updated 4 years ago
- ☆37Updated 4 years ago
- Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.☆63Updated last month
- A simple script to build a PMU firmware for Xilinx ZynqMP☆33Updated last month
- Avnet Board Definition Files☆132Updated 3 months ago
- Fixed Point Math Library for Verilog☆127Updated 10 years ago
- FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq-Zybo:PYNQ-Z1 Altera:de0-nano-soc:de1…☆161Updated last year
- FPGA and Digital ASIC Build System☆74Updated 2 weeks ago
- TCP/IP controlled VPI JTAG Interface.☆65Updated 2 months ago
- Demonstration of the AXI DMA engine on the ZedBoard☆52Updated 4 years ago
- Slides and lab instructions for the mastering MicroBlaze session☆35Updated 2 years ago
- ☆36Updated last year
- Board files to build Ultra 96 PYNQ image☆154Updated 3 months ago
- FuseSoC standard core library☆131Updated last week
- Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)☆43Updated 7 years ago
- ☆108Updated 2 months ago
- A VHDL UART for communicating over a serial link with an FPGA☆73Updated 9 years ago
- ☆62Updated 7 years ago