Alternatives and similar repositories for llvm-or1k

Users that are interested in llvm-or1k are comparing it to the libraries listed below

• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆50Updated 8 years ago
• michaeljclark / riscv-disassembler
  RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC
  ☆99Updated 3 years ago
• TUD-OS / NUL
  NOVA userland
  ☆48Updated 11 years ago
• CTSRD-CHERI / qemu
  QEMU with support for CHERI
  ☆59Updated this week
• CTSRD-CHERI / llvm-project
  Fork of LLVM adding CHERI support
  ☆57Updated last week
• riscvarchive / riscv-lld
  RISC-V port of LLVM Linker
  ☆24Updated 7 years ago
• michaeljclark / riscv-meta
  RISC-V Instruction Set Metadata
  ☆41Updated 6 years ago
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆42Updated 6 years ago
• blitz / kernel_entry_benchmark
  Microbenchmarks for x86_64 kernel entry methods
  ☆19Updated 3 years ago
• ria-jit / ria-jit
  Lightweight and performant dynamic binary translation for RISC–V code on x86–64
  ☆61Updated 4 years ago
• jimix / k42
  K42 Kernel
  ☆29Updated 13 years ago
• shacron / sled
  Sled System Emulator
  ☆28Updated 4 months ago
• ArchC / ArchC
  A powerful and modern open-source architecture description language.
  ☆42Updated 7 years ago
• lcq2 / risc-666
  RISC-V user-mode emulator that runs DooM
  ☆54Updated 6 years ago
• riscvarchive / riscv-fesvr
  RISC-V Frontend Server
  ☆63Updated 6 years ago
• OpenPOWERFoundation / a2i
  The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
  ☆45Updated 3 years ago
• KestrelComputer / S64X7
  64-bit MISC Architecture CPU
  ☆12Updated 8 years ago
• maerhart / llhd
  A low-level intermediate representation for hardware description languages
  ☆28Updated 5 years ago
• TUD-OS / NRE
  NOVA runtime environment (official branch)
  ☆34Updated 4 years ago
• mclinker / mclinker
  LLVM Linker for Mobile Computing
  ☆81Updated 9 years ago
• xiangzhai / dragonegg
  DragonEgg has been migrated to GCC 8 and LLVM 6 but also able to work for GCC 4.8 and LLVM 3.3
  ☆19Updated 6 years ago
• azonenberg / antikernel
  The Antikernel operating system project
  ☆121Updated 5 years ago
• jserv / jit-construct
  JIT compiler from scratch, derived from Nick Desaulniers' great work
  ☆44Updated 4 years ago
• nspin / hs-arm
  (Dis)assembler and analyzer generated from the machine-readable ARMv8.3-A specification
  ☆27Updated 7 years ago
• defparam / higan-verilog
  This is a higan/Verilator co-simulation example/framework
  ☆50Updated 7 years ago
• HobbesOSR / kitten
  Kitten Lightweight Kernel
  ☆56Updated 2 years ago
• hitohira / yokyo
  ☆17Updated 2 years ago
• riscvarchive / riscv-glibc
  RISC-V port of GNU's libc
  ☆71Updated 4 years ago
• tomahawkins / verilog
  A Verilog parser for Haskell.
  ☆36Updated 4 years ago
• avadhpatel / marss
  PTLsim and QEMU based Computer Architecture Research Simulator
  ☆130Updated 3 years ago