openrisc / llvm-or1k

Related projects ⓘ

Alternatives and complementary repositories for llvm-or1k

• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆46Updated 7 years ago
• nlsynth / iroha
  Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)
  ☆35Updated 3 years ago
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆41Updated 5 years ago
• nyuichi / xv6
  xv6 porting to GAIA architecture
  ☆46Updated 9 years ago
• michaeljclark / riscv-meta
  RISC-V Instruction Set Metadata
  ☆39Updated 6 years ago
• michaeljclark / riscv-disassembler
  RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC
  ☆97Updated 2 years ago
• riscvarchive / riscv-fesvr
  RISC-V Frontend Server
  ☆62Updated 5 years ago
• atgreen / moxie-cores
  Moxie-compatible core repository
  ☆45Updated 11 months ago
• srokicki / HybridDBT
  ☆31Updated 4 years ago
• seL4 / refos
  Prototype no-assurance reference OS personality built on seL4
  ☆49Updated 3 years ago
• ucb-bar / esp-llvm
  UCB-BAR fork of LLVM! NOT UPSTREAM RISCV LLVM
  ☆123Updated 3 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆54Updated 7 years ago
• OpenPOWERFoundation / a2o
  The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …
  ☆44Updated 6 months ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆27Updated 2 weeks ago
• lcq2 / risc-666
  RISC-V user-mode emulator that runs DooM
  ☆49Updated 5 years ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆72Updated 2 months ago
• sifive / last-week-in-risc-v
  Weekly RISC-V Newsletter
  ☆28Updated 5 years ago
• acjf3 / l3mips
  L3 based MIPS specification and emulator
  ☆15Updated 3 years ago
• riscvarchive / riscv-glibc
  RISC-V port of GNU's libc
  ☆70Updated 3 years ago
• OpenPOWERFoundation / a2i
  The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
  ☆40Updated 2 years ago
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 7 years ago
• riscv-non-isa / riscv-device-tree-doc
  RISC-V Specific Device Tree Documentation
  ☆41Updated 4 months ago
• KestrelComputer / S64X7
  64-bit MISC Architecture CPU
  ☆11Updated 7 years ago
• riscv / riscv-test-env
  ☆40Updated 5 months ago
• riscvarchive / riscv-musl
  musl libc for RISC-V
  ☆81Updated 5 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated last year
• cliffordwolf / xbitmanip
  RISC-V XBitmanip Extension
  ☆27Updated 5 years ago