Alternatives and similar repositories for uiCA-eval

Users that are interested in uiCA-eval are comparing it to the libraries listed below

• ychen306 / vegen
  ☆31Updated 3 years ago
• mc-imperial / multicore-test-harness
  A multicore microprocessor test harness for measuring interference
  ☆14Updated 5 years ago
• daniellustig / riscv-memory-model
  A formalization of the RVWMO (RISC-V) memory model
  ☆35Updated 3 years ago
• stephand / ptlsim
  Stable, non-KVM version of PTLsim.
  ☆29Updated 9 years ago
• jaopaulolc / KernelFaRer
  KernelFaRer: Replacing Native-Code Idioms with High-Performance Library Calls
  ☆12Updated 3 months ago
• ArchC / ArchC
  A powerful and modern open-source architecture description language.
  ☆46Updated 8 years ago
• caparrov / ERM
  Extended Roofline Model - LLVM source tree with additional libraries for the analysis of the dynamic execution in the interpreter
  ☆17Updated 8 years ago
• makslevental / mmlir
  A minimal (really) out-of-tree MLIR example
  ☆46Updated 4 months ago
• ymanerka / rtlcheck
  RTLCheck
  ☆23Updated 7 years ago
• cliffordwolf / bextdep
  Reference Hardware Implementations of Bit Extract/Deposit Instructions
  ☆25Updated 8 years ago
• openhwgroup / corev-llvm-project
  ☆18Updated last year
• daniellustig / coatcheck
  COATCheck
  ☆13Updated 7 years ago
• Jonathan2251 / lbt
  Develop toolchain based on llvm to for Cpu0 processor
  ☆52Updated last month
• melver / mc2lib
  Memory consistency model checking and test generation library.
  ☆15Updated 9 years ago
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆99Updated this week
• dzaima / intrinsics-viewer
  x86-64, ARM, and RVV intrinsics viewer
  ☆76Updated 3 weeks ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆38Updated 4 years ago
• iree-org / iree-bare-metal-arm
  Example for running IREE in a bare-metal Arm environment.
  ☆40Updated 4 months ago
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆52Updated last week
• johnwickerson / memalloy
  Memory consistency modelling using Alloy
  ☆31Updated 5 years ago
• CTSRD-CHERI / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆34Updated this week
• rutgers-apl / fpsanitizer
  A debugger to detect and diagnose numerical errors in floating point programs
  ☆12Updated 3 years ago
• daniellustig / pipecheck
  ☆19Updated 10 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• maerhart / llhd
  A low-level intermediate representation for hardware description languages
  ☆28Updated 5 years ago
• aqjune / mlir-tv
  A translation validation framework for MLIR
  ☆89Updated 9 months ago
• CTSRD-CHERI / llvm-project
  Fork of LLVM adding CHERI support
  ☆60Updated this week
• SiliconSemantics / firrtlator
  firrtlator is a FIRRTL C++ library
  ☆23Updated 9 years ago
• kitbarton / LLVMLoopOptTutorial
  Tutorial for LLVM Dev Conference 2019.
  ☆15Updated 6 years ago
• intel / vc-intrinsics
  ☆59Updated this week