michaelliao / learn-verilog
Learn Verilog
☆35Updated 2 years ago
Alternatives and similar repositories for learn-verilog:
Users that are interested in learn-verilog are comparing it to the libraries listed below
- An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.☆60Updated 2 years ago
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆36Updated 3 years ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆26Updated last year
- Peripheral Interface of FPGA☆34Updated 3 years ago
- 8051 core☆103Updated 10 years ago
- a riscv32 rv32imc emulator written in c.☆33Updated 6 months ago
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆78Updated 4 years ago
- 用Altera FPGA芯片自制CPU☆41Updated 10 years ago
- Yet another free 8051 FPGA core☆33Updated 6 years ago
- 基于ALINX-AX7020平台的Linux驱动开发学习。☆45Updated 4 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆49Updated 8 months ago
- Cortex_m0软核源码,可以在FPGA上直接跑,包含UART、定时器这些外设,可以用keil写用户代码。可以看看《Cortex-M0 全可编程SoC原理及实现》这本书☆23Updated 4 years ago
- a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog☆23Updated last year
- A RISCV Emulator written in Python☆45Updated 2 years ago
- Nuclei Board Labs☆57Updated last year
- A 32bit RISC-V SoC on FPGA (EG4S20) that supports RT-Thread.☆12Updated 4 years ago
- LoveLonelyTime's RISC-V core basic version, RV32I, five pipeline stages.☆17Updated 11 months ago
- Verilog极简教程☆35Updated 5 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆31Updated 4 years ago
- ☆32Updated 2 years ago
- ☆31Updated this week
- As a salute to the guy who inspired me to become EE engineer. This is the RTL version of his homebrew CPU core (KC-LS1u)☆16Updated last year
- OV7670 (Verilog HDL)Drive for FPGA☆15Updated 6 years ago
- DDR4 Simulation Project in System Verilog☆34Updated 10 years ago
- OpenMIPS——《自己动手写CPU》处理器部分☆22Updated 8 years ago
- Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-…☆30Updated 4 years ago
- ☆18Updated 4 years ago
- Simple RV32I simulator in C☆19Updated last year
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆103Updated 2 years ago
- fpga based nes box☆29Updated 3 years ago