Alternatives and similar repositories for DeSCAM

Users that are interested in DeSCAM are comparing it to the libraries listed below

• amiq-consulting / uvm_reg_to_ipxact
  ☆15Updated 6 years ago
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆10Updated 5 years ago
• Doulos / SystemC-Engine
  Explore the behavior SystemC kernel event-driven simulator (aka "the engine")
  ☆11Updated last year
• ben-marshall / verilog-doc
  A basic documentation generator for Verilog, similar to Doxygen.
  ☆11Updated 8 years ago
• tudortimi / ipxact
  IP-XACT XML binding library
  ☆16Updated 8 years ago
• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆24Updated 4 years ago
• vlotnik / uvm_modem
  UVM components for DSP tasks (MODulation/DEModulation)
  ☆14Updated 3 years ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆38Updated last week
• kactus2 / ipxactexamplelib
  Contains examples to start with Kactus2.
  ☆18Updated 10 months ago
• Risto97 / systemc_uvm_verilator
  ☆12Updated 2 years ago
• tudortimi / vpi
  SystemVerilog wrapper over the Verilog Programming Interface (VPI)
  ☆13Updated this week
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• drom / sta
  🕒 Static Timing Analysis diagram renderer
  ☆13Updated last year
• TUK-SCVP / SCVP.artifacts
  Artifacts for the SCVP lecture
  ☆10Updated 3 years ago
• fvutils / vte
  Verification Template Engine is a Jinja2-based template engine targeted at verification engineers
  ☆13Updated last year
• amiq-consulting / fc4sc
  A header only C++11 library for functional coverage
  ☆36Updated 2 years ago
• tudortimi / reflection
  Reflection API for SystemVerilog
  ☆14Updated 3 weeks ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• pybfms / pybfms
  Provides automation scripts for building BFMs
  ☆16Updated last month
• go2uvm / go2uvm
  Main repo for Go2UVM source code, examples and apps
  ☆21Updated 2 years ago
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 5 years ago
• TILhub / AMBA-3-AHB-Lite-Protocol
  This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol
  ☆13Updated 6 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 2 years ago
• Mochenx / sv_csv_parser
  A CSV file parser, written in SystemVerilog
  ☆26Updated 8 years ago
• ben-marshall / verilog-dot
  A simple dot file / graph generator for Verilog syntax trees.
  ☆22Updated 8 years ago
• bogdanvuk / sydpy
  System Design in Python (SyDPy) is a tool for design and verification of concurrent systems. The tool is offered as an alternative to Sys…
  ☆12Updated 9 years ago
• NJDFan / register-maps
  Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.
  ☆12Updated 2 years ago
• ganeshgore / spydrnet-physical
  This is a SpyDrNet Plugin for a physical design related transformations
  ☆12Updated this week
• seabeam / yuu_clock
  UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available
  ☆10Updated 4 years ago
• edaa-org / IPXACT-Schema
  This repository provides the IEEE 1685 IP-XACT schema files for a Git submodule integration.
  ☆18Updated 3 weeks ago