freecores / avr_core
AVR Core
☆12Updated 10 years ago
Alternatives and similar repositories for avr_core:
Users that are interested in avr_core are comparing it to the libraries listed below
- ULPI Link Wrapper (USB Phy Interface)☆25Updated 4 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆61Updated 6 years ago
- ESP8266 powered Xilinx Virtual Cable - Xilinx WiFi JTAG!☆24Updated 3 years ago
- PCB combining Raspberry Pi Pico and iCE40 FPGA☆32Updated 9 months ago
- Example designs for the Spartan7 "S7 Mini" FPGA board☆28Updated 5 years ago
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Updated 6 years ago
- Test code to talk from STM32 MCU over FSMC to SDRAM on ICE40 FPGA☆26Updated 8 years ago
- 🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.☆23Updated 3 years ago
- ☆18Updated 4 years ago
- FPGA implementation of DSITx (single lane) used in conjunction with ipod nano 7th gen display☆20Updated 6 years ago
- WISHBONE Builder☆14Updated 8 years ago
- turbo 8051☆28Updated 7 years ago
- Xilinx 7-series FTDI-FPGA interface through JTAG with 125 us roundtrip latency☆19Updated 5 years ago
- WCH CH569 SerDes Reverse Engineering☆26Updated 2 years ago
- FTDI EEPROM User Area Writer For Xilinx JTAG Programmer☆12Updated 11 years ago
- Client for JTAG programmer for AVR microcontrollers☆14Updated 11 months ago
- SDRAM controller with multiple wishbone slave ports☆28Updated 6 years ago
- Xilinx virtual cable daemon j-link support☆19Updated 8 years ago
- USB serial device (CDC-ACM)☆37Updated 4 years ago
- Connecting FPGA and MCU using Ethernet RMII☆22Updated 9 years ago
- Simplified environment for litex☆14Updated 4 years ago
- USB Full Speed PHY☆39Updated 4 years ago
- A flexible, simple, yet powerful FPGA development board.☆15Updated 7 years ago
- USB3 super speed development board useful as FPGA expansion based on WCH-Tech CH569☆25Updated 2 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆12Updated 6 years ago
- AGM bitstream utilities and decoded files from Supra☆41Updated 10 months ago
- Communication channel from FPGA (Alterra EP4CE10) and Linux (Lichee PI Allwinner V3S)☆28Updated 4 years ago
- Example Verilog code for Ulx3s☆40Updated 2 years ago
- usb-jtag - Altera USB Blaster Emulation with a FX2☆70Updated 3 years ago
- Mega/Xmega soft core RTL design.☆11Updated 4 years ago