chethiya / Deep-Learning-Processor-List
A list of ICs and IPs for AI, Machine Learning and Deep Learning.
☆21Updated 6 years ago
Related projects: ⓘ
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆32Updated 4 years ago
- ☆22Updated 7 years ago
- Compiler toolkit for neuFlow.☆26Updated 11 years ago
- Binary Neural Network on IceStick FPGA.☆48Updated 6 years ago
- OpenCL Demos for Xilinx FPGAs☆31Updated 8 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 3 years ago
- OpenDLA for trying the demo and FPGA solution☆15Updated 2 years ago
- NVDLA modifications for GreenSocs qbox (https://git.greensocs.com/qemu/qbox)☆19Updated 6 years ago
- a clone of POCL that includes RISC-V newlib devices support and Vortex☆36Updated 3 months ago
- Using Verilog to implement the SIFT algorithm into an FPGA for small robotic situations☆35Updated 10 years ago
- Benchmarking Analysis of Vision Kernels on Embedded CPU, GPU and FPGA☆14Updated 5 years ago
- ☆42Updated 2 years ago
- Driver stack (including user space libraries, kernel module and firmware) for the Arm® Ethos™-N NPU☆57Updated last month
- NVDLA modifications for GreenSocs models/simple_cpu (https://git.greensocs.com/models/simple_cpu)☆17Updated 6 years ago
- TF Lite demo on LiteX/VexRiscv soft RISC-V SoC on a Digilent Arty board☆62Updated 2 years ago
- Example code and instructions on getting Tensorflow Lite running on a Xilinx Zynq☆49Updated 6 years ago
- DyRACT Open Source Repository☆16Updated 8 years ago
- RISC-V GPGPU☆34Updated 4 years ago
- ☆29Updated this week
- ☆20Updated 9 months ago
- EEMBC's Machine-Learning Inference Benchmark targeted at edge devices.☆45Updated 2 years ago
- ☆26Updated this week
- Parallel Array of Simple Cores. Multicore processor.☆92Updated 5 years ago
- An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.☆46Updated 10 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆38Updated 8 years ago
- CMSIS DSP Library for PULPino microcontroller☆22Updated 6 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- ☆39Updated 7 years ago
- Artificial Neural Network on Altera DE2☆32Updated 8 years ago
- Lightweight C implementation of CNNs for Embedded Systems☆53Updated last year