chethiya / Deep-Learning-Processor-List
A list of ICs and IPs for AI, Machine Learning and Deep Learning.
☆23Updated 6 years ago
Alternatives and similar repositories for Deep-Learning-Processor-List
Users that are interested in Deep-Learning-Processor-List are comparing it to the libraries listed below
Sorting:
- Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs☆17Updated 4 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆39Updated 9 years ago
- Using Verilog to implement the SIFT algorithm into an FPGA for small robotic situations☆39Updated 11 years ago
- Neural Engine, 16 input channels☆13Updated 2 years ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆35Updated 5 years ago
- High Throughput Image Filters on FPGAs☆13Updated 7 years ago
- Public resources available for Xilinx MPSOC+ and SDSOC hardware☆18Updated 7 years ago
- Xilinx Soft-IP HDMI Rx/Tx core Linux drivers☆42Updated 2 weeks ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- OpenCL Demos for Xilinx FPGAs☆31Updated 9 years ago
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆19Updated last week
- OpenDLA for trying the demo and FPGA solution☆16Updated 2 years ago
- Yocto project for Xuantie RISC-V CPU☆38Updated this week
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Formerly known as the 'reVISION Getting Started Guide', the Embedded Reference Platforms User Guide covers the embedded vision reference …☆11Updated last year
- Who doesn’t dream of a new FPGA family that can provide embedded hard neurons in its silicon architecture fabric instead of the conventio…☆16Updated 6 years ago
- ☆46Updated 5 years ago
- Gate-Level Simulation on a GPU☆10Updated 8 years ago
- Real-Time Image Processing for ASIC/FGPA☆16Updated 3 years ago
- NVDLA modifications for GreenSocs models/simple_cpu (https://git.greensocs.com/models/simple_cpu)☆20Updated 6 years ago
- DyRACT Open Source Repository☆16Updated 9 years ago
- ☆19Updated last year
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- a clone of POCL that includes RISC-V newlib devices support and Vortex☆42Updated last month
- ☆33Updated 2 years ago
- A real time Histogram of Oriented Gradients Implementation on FPGA☆32Updated 6 years ago
- Ubuntu 18.04 Desktop for Ultra96/Ultra96-V2☆19Updated 5 years ago
- Another tiny RISC-V implementation☆55Updated 3 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆29Updated 4 months ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆23Updated last week