dag10 / Logisim_CPU
Made a CPU in Logisim when I was 14 (2009), and wrote a naive assembler and compiler for it in Flash. The CPU's design is inspired by Donn Stewart, http://cpuville.com.
☆12Updated 8 years ago
Alternatives and similar repositories for Logisim_CPU:
Users that are interested in Logisim_CPU are comparing it to the libraries listed below
- 64-bit MISC Architecture CPU☆12Updated 8 years ago
- ☆20Updated 12 years ago
- Logisim CPU.☆31Updated 2 years ago
- A collection of little open source FPGA hobby projects☆48Updated 5 years ago
- YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…☆44Updated 3 months ago
- Portable C Compiler (CVS mirror)☆11Updated 12 years ago
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆53Updated 3 years ago
- a simple C-to-Verilog compiler☆48Updated 7 years ago
- An online Verilog IDE based on YosysJS.☆24Updated 9 years ago
- System on Chip SPARC V8 using leon3 CPU by Gaisler. C++, vhdl, v files.☆11Updated 12 years ago
- Tiny CPU is a small 32-bit CPU done mostly as a hobby for educational purposes.☆32Updated 13 years ago
- Here is a bunch of util IPs☆10Updated 6 years ago
- Graphical user interface for circuit simulation on GNU/Linux using ngspice☆16Updated 8 years ago
- Raspberry PI barebones kernel.☆20Updated 12 years ago
- An executable specification of the RISCV ISA in L3.☆41Updated 6 years ago
- A C to verilog compiler☆52Updated 9 years ago
- LLVM backend for dcpu-16 processor☆213Updated 8 years ago
- RISC-V strace port☆13Updated 8 years ago
- RTOS based on L4 microkernel.☆16Updated 6 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆39Updated 9 years ago
- ☆27Updated 5 years ago
- A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.☆35Updated 2 years ago
- USB 1.1 Device IP Core☆20Updated 7 years ago
- newlib OpenRISC development☆25Updated 3 years ago
- Work towards a "golden model" of the RISC-V calling convention(s)☆10Updated 7 years ago
- historical clone from geda-project☆15Updated 5 months ago
- Parser of C-syntax data definitions, C-syntax function definitions☆20Updated 12 years ago
- rv6 is a kernel & operating system written entirely in rust.☆11Updated 5 years ago
- RISC-V port of LLVM Linker☆24Updated 6 years ago
- StickIt! board and modules that support the XuLA FPGA board.☆20Updated 9 years ago