dag10 / Logisim_CPU
Made a CPU in Logisim when I was 14 (2009), and wrote a naive assembler and compiler for it in Flash. The CPU's design is inspired by Donn Stewart, http://cpuville.com.
☆12Updated 8 years ago
Alternatives and similar repositories for Logisim_CPU:
Users that are interested in Logisim_CPU are comparing it to the libraries listed below
- 64-bit MISC Architecture CPU☆12Updated 8 years ago
- Design with Logisim a 32-bit two-cycle processor☆9Updated 9 years ago
- An online Verilog IDE based on YosysJS.☆24Updated 9 years ago
- RISC-V port of LLVM Linker☆24Updated 6 years ago
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆53Updated 3 years ago
- a simple C-to-Verilog compiler☆48Updated 8 years ago
- A collection of little open source FPGA hobby projects☆48Updated 5 years ago
- historical clone from geda-project☆16Updated 2 weeks ago
- YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…☆45Updated 4 months ago
- The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.☆28Updated 3 years ago
- A reimplementation of a tiny stack CPU☆82Updated last year
- Logisim CPU.☆32Updated 2 years ago
- Icestorm, Arachne-pnr and Yosys pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS☆38Updated 2 years ago
- ☆51Updated 8 years ago
- A wishbone controlled FM transmitter hack☆22Updated last year
- Portable C Compiler (CVS mirror)☆12Updated 13 years ago
- A small, microcoded RISC-V processor.☆9Updated 8 years ago
- IP cores for the FPGA Libre project☆12Updated 7 years ago
- An 8-bit CPU designed for education☆22Updated 10 years ago
- A pipelined brainfuck softcore in Verilog☆18Updated 10 years ago
- System on Chip SPARC V8 using leon3 CPU by Gaisler. C++, vhdl, v files.☆11Updated 12 years ago
- A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.☆35Updated 2 years ago
- newlib OpenRISC development☆25Updated 3 weeks ago
- The directory to save GD32VF103 DataSheets☆19Updated 4 years ago
- Port of the Yocto Project to the RISC-V ISA☆62Updated 6 years ago
- Enigma in FPGA☆29Updated 5 years ago
- RISC-V instruction set CPUs in HardCaml☆15Updated 8 years ago
- Minimal microprocessor☆20Updated 7 years ago
- AXI MIPI CSI2 RX FPGA core and kernel driver☆8Updated 9 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆39Updated 9 years ago