dag10 / Logisim_CPULinks
Made a CPU in Logisim when I was 14 (2009), and wrote a naive assembler and compiler for it in Flash. The CPU's design is inspired by Donn Stewart, http://cpuville.com.
☆12Updated 9 years ago
Alternatives and similar repositories for Logisim_CPU
Users that are interested in Logisim_CPU are comparing it to the libraries listed below
Sorting:
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆53Updated 4 years ago
- Logisim CPU.☆32Updated 2 years ago
- An experimental System-on-Chip with a custom compiler toolchain.☆60Updated 5 years ago
- Port of the Yocto Project to the RISC-V ISA☆61Updated 6 years ago
- 64-bit MISC Architecture CPU☆12Updated 8 years ago
- LEON2 SPARC CPU IP core LGPL by Gaisler Research☆19Updated 12 years ago
- Minimal microprocessor☆21Updated 8 years ago
- The Easy 8-bit Processor☆183Updated 11 years ago
- Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools☆126Updated 9 years ago
- The BERI and CHERI processor and hardware platform☆50Updated 8 years ago
- JOP is a Java processor for real-time systems☆127Updated 11 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- Graphical user interface for circuit simulation on GNU/Linux using ngspice☆17Updated 9 years ago
- Tiny CPU is a small 32-bit CPU done mostly as a hobby for educational purposes.☆35Updated 13 years ago
- A RISC-V CPU (Outdated: using priviledge v1.7)☆25Updated 6 years ago
- RISC-V Frontend Server☆63Updated 6 years ago
- MRSIC32 ISA documentation and development☆91Updated 2 years ago
- A MIPS32 CPU implemented by VHDL☆30Updated 12 years ago
- A user-expandable micro-computer system that runs on an FPGA development board and includes the FORTH software language. The system is cu…☆28Updated last week
- A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.☆36Updated 3 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆41Updated 9 years ago
- IP cores for the FPGA Libre project☆12Updated 8 years ago
- ☆26Updated 6 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- Human Resource Machine - CPU Design #HRM☆76Updated 2 months ago
- Linux kernel source tree☆35Updated this week
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆55Updated 6 years ago
- UCB-BAR fork of LLVM! NOT UPSTREAM RISCV LLVM☆122Updated 4 years ago
- RISC-V port of newlib☆100Updated 3 years ago
- Git Mirror of Yann Morin's kconfig-frontends project☆19Updated 12 years ago