dag10 / Logisim_CPULinks
Made a CPU in Logisim when I was 14 (2009), and wrote a naive assembler and compiler for it in Flash. The CPU's design is inspired by Donn Stewart, http://cpuville.com.
☆10Updated 9 years ago
Alternatives and similar repositories for Logisim_CPU
Users that are interested in Logisim_CPU are comparing it to the libraries listed below
Sorting:
- Logisim CPU.☆33Updated 3 years ago
- ReconOS - Operating System for Reconfigurable Hardware☆29Updated 4 years ago
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆54Updated 4 years ago
- MRSIC32 ISA documentation and development☆91Updated 2 years ago
- Tiny CPU is a small 32-bit CPU done mostly as a hobby for educational purposes.☆35Updated 14 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- The Easy 8-bit Processor☆187Updated 11 years ago
- VHDL Samples☆70Updated 13 years ago
- Regression test suite for Icarus Verilog. (OBSOLETE)☆115Updated 2 years ago
- Minimal microprocessor☆21Updated 8 years ago
- An experimental System-on-Chip with a custom compiler toolchain.☆60Updated 6 years ago
- Port of the Yocto Project to the RISC-V ISA☆60Updated 7 years ago
- RISC-V port of GNU's libc☆72Updated 4 years ago
- 64-bit MISC Architecture CPU☆13Updated 9 years ago
- Everything to do with the XuLA FPGA board: schematics, layout, firmware, example FPGA designs, documentation, etc.☆37Updated 11 years ago
- a simple C-to-Verilog compiler☆51Updated 8 years ago
- RISC-V port of newlib☆102Updated 3 years ago
- Verilog implementation of pipelined cpu☆12Updated 5 years ago
- Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools☆126Updated 9 years ago
- A MIPS32 CPU implemented by VHDL☆30Updated 12 years ago
- RISC-V Frontend Server☆64Updated 6 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆41Updated 10 years ago
- The OpenRISC 1000 architectural simulator☆77Updated 9 months ago
- The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.☆28Updated 3 years ago
- Open Processor Architecture☆26Updated 9 years ago
- LatticeMico32 soft processor☆107Updated 11 years ago
- The BERI and CHERI processor and hardware platform☆50Updated 8 years ago
- Git Mirror of Yann Morin's kconfig-frontends project☆19Updated 12 years ago
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆91Updated 5 years ago
- LEON2 SPARC CPU IP core LGPL by Gaisler Research☆20Updated 12 years ago