Alternatives and similar repositories for 32-bit-CPU:

Users that are interested in 32-bit-CPU are comparing it to the libraries listed below

• vivianliu / Logisim-Processor
  Designing a 32-bit MIPS CPU in Logisim
  ☆11Updated 13 years ago
• dag10 / Logisim_CPU
  Made a CPU in Logisim when I was 14 (2009), and wrote a naive assembler and compiler for it in Flash. The CPU's design is inspired by Don…
  ☆12Updated 8 years ago
• riscvarchive / riscv-lld
  RISC-V port of LLVM Linker
  ☆24Updated 6 years ago
• riscvarchive / riscv-glibc
  RISC-V port of GNU's libc
  ☆70Updated 4 years ago
• riscvarchive / riscv-poky
  Port of the Yocto Project to the RISC-V ISA
  ☆62Updated 6 years ago
• riscvarchive / riscv-fesvr
  RISC-V Frontend Server
  ☆63Updated 6 years ago
• devanshdalal / Logisim-CPU-processor
  A Simple 5-stage CPU pipeline simulator using Logisim
  ☆9Updated 9 years ago
• BYVoid / MIPS32
  A MIPS32 CPU implemented by VHDL
  ☆30Updated 11 years ago
• michaeljclark / busybear-linux
  busybear-linux is a tiny RISC-V Linux root filesystem image that targets the VirtIO board in riscv-qemu.
  ☆98Updated 9 months ago
• tqyaaaaang / Hyper-OS
  Operating System Simulator
  ☆19Updated 5 years ago
• skyzh / mips-simulator
  💻 A 5-stage pipeline MIPS CPU design in Haskell.
  ☆36Updated 4 years ago
• wuxx / sos
  Simple OS for raspberry pi 2 model B
  ☆14Updated 7 years ago
• riscvarchive / documents
  riscv.github.io
  ☆11Updated 4 years ago
• adumont / hrm-cpu
  Human Resource Machine - CPU Design #HRM
  ☆75Updated 4 years ago
• oscourse-tsinghua / rcore_plus
  Rust version of THU uCore OS. Linux compatible.
  ☆172Updated 4 years ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆82Updated 4 years ago
• riscv-software-src / riscv-config
  RISC-V Configuration Validator
  ☆77Updated 3 weeks ago
• XianBeiTuoBaFeng2015 / MySlides
  My Slides
  ☆17Updated last year
• tcr / rust-verilog
  Verilog parsing and generator crate.
  ☆21Updated 5 years ago
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• riscvarchive / riscv-newlib
  RISC-V port of newlib
  ☆96Updated 3 years ago
• openrisc / newlib
  newlib OpenRISC development
  ☆25Updated 3 weeks ago
• SanDisk-Open-Source / riscv-fw-infrastructure
  Firmware infrastructure, contain RTOS Abstraction Layer, demos and more...
  ☆53Updated 3 years ago
• Harry-Chen / rust-mips
  Rust library for low-level abstraction of MIPS processors
  ☆31Updated 4 years ago
• lxp32 / lxp32-cpu
  A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
  ☆60Updated 4 months ago
• jingjin666 / GN-base
  ☆11Updated 2 months ago
• mattstock / bexkat1
  An experimental CPU design
  ☆15Updated 5 years ago
• riscv-rust / riscv-rust-toolchain
  RISCV Rust Toolchain
  ☆117Updated 6 years ago
• SimpleCPU / SimpleCPU
  An open source CPU design and verification platform for academia
  ☆101Updated 4 years ago
• gmish27 / CPUonFPGA
  It's a basic computer designed using VERILOG on XILINX FPGA architecture.
  ☆16Updated 8 years ago