anishathalye / knox-hsm
Circuits and hardware security modules formally verified with Knox 🔐
☆24Updated 8 months ago
Related projects ⓘ
Alternatives and complementary repositories for knox-hsm
- A framework for formally verifying hardware security modules to be free of hardware, software, and timing side-channel vulnerabilities 🔏☆33Updated last year
- XCrypto: a cryptographic ISE for RISC-V☆92Updated last year
- Optimized assembly implementations of crypto for the RV32I (RISC-V) architecture☆31Updated 4 years ago
- cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.☆78Updated 3 weeks ago
- ☆10Updated last year
- Verifying OpenTitan☆22Updated last year
- Crypto library☆52Updated last month
- Assured confidential execution (ACE) implements VM-based trusted execution environment (TEE) for RISC-V with focus on a formally verified…☆31Updated last month
- Testing processors with Random Instruction Generation☆29Updated last month
- This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…☆42Updated this week
- Side-Channel Analysis Library☆74Updated 2 months ago
- CHERI-RISC-V model written in Sail☆55Updated last week
- Security monitor for Keystone Enclave (mirror of riscv-pk). Will be deprecated when openSBI port is ready☆36Updated 3 years ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆21Updated last month
- Notary: A Device for Secure Transaction Approval 📟☆28Updated last year
- Side-channel analysis setup for OpenTitan☆28Updated 2 months ago
- Exploring the Ed25519 (FPGA) design space.☆16Updated 6 years ago
- Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.☆125Updated 2 years ago
- High-order countermeasures for AES and DES☆25Updated 3 months ago
- RISC-V BSV Specification☆17Updated 4 years ago
- ☆17Updated 6 months ago
- Module-Lattice-based Digital Signature Standard (draft) standard by NIST☆36Updated 3 months ago
- Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model☆71Updated last month
- Hardware implementation of ORAM☆22Updated 7 years ago
- A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI☆29Updated this week
- SLotH -- An SLH-DSA/SPHINCS+ Hash-Based Signature Accelerator☆22Updated last month
- OpenMZ, a security kernel for RISC-V targeting secure coprocessors and secure embedded systems.☆12Updated 4 years ago
- PROLEAD - A Probing-Based Leakage Detection Tool for Hardware and Software☆32Updated this week
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆35Updated 3 years ago
- A bitsliced implementation of ECB and CTR AES☆46Updated 3 months ago