bobbl / punycc

Related projects ⓘ

Alternatives and complementary repositories for punycc

• ElEctric-EyE / verilog-6502
  This fork family includes the 6502 upgraded to 32-bit address bus, in Verilog HDL
  ☆20Updated 4 years ago
• Anding / N.I.G.E.-Machine
  A user-expandable micro-computer system that runs on an FPGA development board and includes the FORTH software language. The system is cu…
  ☆26Updated 5 years ago
• jbush001 / MiteCPU
  Minimal microprocessor
  ☆19Updated 7 years ago
• Obijuan / j1a-icestudio
  SwapForth J1a processor for Icestudio
  ☆12Updated 4 years ago
• revaldinho / opc
  One Page CPU Project - CPU, Assembler & Emulator each in a single page of code
  ☆80Updated 4 months ago
• rob-ng15 / Silice-Playground
  Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice
  ☆34Updated last year
• Mr-Bossman / KISC-V
  KISCV, a KISS principle riscv32i CPU
  ☆20Updated 2 months ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆36Updated last year
• tommythorn / tinytapeout-4-bit-cpu
  A design for TinyTapeout
  ☆15Updated 2 years ago
• samawati / j1eforth
  eForth for the j1 simulator and actual J1 FPGAs
  ☆32Updated 9 years ago
• grayresearch / s3ga
  S3GA: a simple scalable serial FPGA
  ☆10Updated last year
• Mecrisp / Nandland-RISC-V
  RISC-V Playground on Nandland Go
  ☆14Updated last year
• hutch31 / tv80
  TV80 Z80-compatible microprocessor
  ☆46Updated 4 years ago
• GuzTech / shdl6800
  shdl6800: A 6800 processor written in SpinalHDL
  ☆26Updated 4 years ago
• sellicott / tcc-riscv32
  Port TCC (Tiny C Compiler) to support Risc-V 32 targets (specifically for the ESP32-C3). This project is a work-in-progress and is not cu…
  ☆61Updated last year
• lipro / tv80
  The TV80 (Verilog) synthesizable soft core of Zilog Z80 (forked from http://opencores.org/project,tv80)
  ☆9Updated 8 years ago
• monsonite / Bit-Serial-ALU
  Simulations and designs for bit serial ALU implemented in TTL circuitry. Also bit serial cpu architectures - all simulated using H. Neem…
  ☆11Updated 2 years ago
• FPGAwars / FLIX-V
  FLIX-V: FPGA, Linux and RISC-V
  ☆41Updated last year
• mrisc32 / mrisc32-a1
  A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA
  ☆22Updated last year
• mcmenaminadrian / riscyforth
  Forth for RISC-V SBCs
  ☆28Updated this week
• fontamsoc / pu32
  ☆15Updated last year
• fredrequin / fpga_1943
  Verilog re-implementation of the famous CAPCOM arcade game
  ☆27Updated 5 years ago
• lisper / cpus-pdp11
  FPGA based PDP-11 cpu
  ☆18Updated 8 years ago
• jevinskie / riscv-smol-linux-kernel
  Patched sources/configs for RISC-V Linux with musl-based toolchain targeting 8 MB RAM
  ☆25Updated 2 years ago
• AntonMause / rv16poc
  16 bit RISC-V proof of concept
  ☆18Updated 2 months ago
• Obijuan / Z80-FPGA
  Z80 CPU for OpenFPGAs, with Icestudio
  ☆75Updated 5 months ago
• machdyne / qqspi
  QQSPI Pmod-compatible 32MB PSRAM module
  ☆14Updated last year
• lawrie / blackicemxbook
  ☆25Updated 4 years ago
• microCore-VHDL / microCore
  Hardware/Software Co-design environment of a processor core for deterministic real time systems
  ☆37Updated last year