gmish27 / CPUonFPGALinks
It's a basic computer designed using VERILOG on XILINX FPGA architecture.
☆15Updated 8 years ago
Alternatives and similar repositories for CPUonFPGA
Users that are interested in CPUonFPGA are comparing it to the libraries listed below
Sorting:
- An attempt at a small Verilog implementation of the original Apple 1 on an FPGA☆146Updated 3 weeks ago
- This fork family includes the 6502 upgraded to 32-bit address bus, in Verilog HDL☆20Updated 12 years ago
- ☆44Updated last month
- 16-bit CPU written in VHDL☆20Updated 6 years ago
- Version 2 of my Crazy Small CPU☆71Updated 6 years ago
- Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu☆23Updated 7 years ago
- Simple SDRAM Controller for DE10-Lite.☆13Updated 6 years ago
- port of Stephen A. Edwards apple2fpga to ULX3S☆17Updated last year
- An implementation of the Z80 CPU for Altera, Xilinx and Lattice FPGAs☆160Updated 5 years ago
- VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)☆36Updated 6 years ago
- Microprogrammed 65C02-compatible FPGA Processor Core (Verilog-2001)☆55Updated 9 years ago
- A CPU on an FPGA that you can play Zork on☆50Updated 8 years ago
- PDP-11/70 CPU core and SoC☆138Updated last year
- QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.☆75Updated last year
- Enhanced 6502/65C02 Microprogrammed FPGA Processor Core (Verilog-2001)☆33Updated 3 years ago
- 65C02 microprocessor in verilog, small size,reduced cycle count, asynchronous interface☆73Updated 2 years ago
- A very primitive but hopefully self-educational CPU in Verilog☆148Updated 10 years ago
- Design and implementation of a complete ARM based CPU.☆15Updated 7 years ago
- Custom 64-bit pipelined RISC processor☆18Updated last year
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆80Updated 6 years ago
- An experimental CPU design☆14Updated 5 years ago
- Pinky (8-bit CPU) written in Verilog and an Assembler written in Python 3☆19Updated 7 years ago
- ☆74Updated 3 months ago
- Reverse engineering the XC2064 FPGA☆81Updated 4 years ago
- Simple fixed-cycle SDRAM Controller☆28Updated 5 years ago
- TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. De…☆149Updated 9 years ago
- The RCA 1802 in Verilog☆21Updated 9 months ago
- This fork family includes the 6502 upgraded to 32-bit address bus, in Verilog HDL☆20Updated 5 years ago
- All code found on nandland is here. underconstruction.gif☆348Updated 3 years ago
- A huge collection of VHDL/Verilog open-source IP cores scraped from the web☆526Updated 2 years ago